Wafer-Bonded Memory Chip Interface With Stress-Absorbing Buffer Layer

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Solution Overview

Problem

The process of bonding wafers in memory devices often results in uneven attachment or gaps, leading to process defects and deterioration of device characteristics.

Innovation Solution

A memory device design that includes a first and second semiconductor chip with bonding insulating layers and a through contact, where a buffer layer is disposed within the opening regions of these layers to absorb stress and prevent delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If wafers are bonded together to achieve high integration, then device functionality is improved, but bonding defects such as uneven attachment and gaps occur

Engineering Contradiction:
Improvedevice functionalityVSAvoidbonding quality
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

A buffer layer is introduced as an intermediary between the first and second bonding insulating layers. This buffer layer fills the opening regions and provides a transition zone that absorbs bonding stress, prevents delamination, and eliminates gaps between the bonded wafers, thereby resolving the bonding quality issues while maintaining device functionality

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The buffer layer is disposed beforehand within the opening regions of the bonding insulating layers before the bonding process is completed. This pre-positioned buffer layer acts as a cushion that absorbs potential bonding stresses and prevents defects from occurring during the bonding process, ensuring uniform attachment without gaps

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Ease of manufacture

If wafer bonding is performed without opening regions, then process simplicity is maintained, but stress accumulation and delamination occur

Engineering Contradiction:
Improveprocess simplicityVSAvoidbonding interface strength
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The bonding insulating layers are segmented by creating opening regions that expose the buffer layer. This segmentation allows the buffer layer to be directly exposed at the bonding interface, enabling stress absorption and prevention of delamination while maintaining a relatively simple overall process flow

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If the opening region width is equal to the through contact width, then manufacturing precision is maintained, but stress concentration and delamination occur

Engineering Contradiction:
Improvedimensional accuracyVSAvoidbonding interface reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The opening regions are designed with a width greater than the through contact width, creating a local quality difference. This larger opening region allows the buffer layer to be fully exposed and provides sufficient space for stress distribution, preventing stress concentration and delamination at the bonding interface while maintaining overall manufacturing precision

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents delamination and maintains device integrity by absorbing stress at the bonding interface, thereby improving the performance and reliability of the memory device.

Implementation Method 1

a buffer layer disposed within the bonding insulating layer... absorbing stress and prevent delamination

Methodology Applied
Scientific EffectStress absorption: Absorption (physical)

Data Source

PatentUS20260068755A1Memory device
Publication Date: 2026.03.05 SK HYNIX INC
  • US20260068755A1 patent drawing
  • US20260068755A1 patent drawing
  • US20260068755A1 patent drawing

AI summary

According to an embodiment of the present disclosure, a memory device may include a first semiconductor chip including a first bonding insulating layer, a second semiconductor chip bonded to the first semiconductor chip, and including a second bonding insulating layer, and a through contact extending from an interior of the first semiconductor chip to an interior of the second semiconductor chip and penetrating at least one opening region of the first bonding insulating layer and the second bonding insulating layer. A width of the opening region may be greater than a width of the through contact.