3D Memory Bonding Pad Layout for Stronger Wafer Interconnects
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Solution Overview
Problem
The integration degree of semiconductor devices is limited by the area occupied by unit memory cells, and there is a need for improved operation reliability in three-dimensional semiconductor devices with stacked memory cells.
Innovation Solution
A semiconductor device with a bonding pad comprising first and second portions of different widths, where a bonding via extends partially inside the first portion, and a bonding layer is used to increase electrical connectivity and bonding force between wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bonding pad with uniform width is used in conventional semiconductor devices, then the manufacturing process is simple, but the electrical connectivity and bonding force between wafers are insufficient
Solution Approach 1:
The bonding pad is designed with an asymmetric width structure, where the first portion has a first width and the second portion has a second width different from the first width. This asymmetric design increases the bonding area and electrical connectivity between wafers while maintaining manufacturing feasibility through standard photolithography processes.
Solution Approach 2:
The bonding pad structure extends in the width dimension with two distinct portions, creating a multi-dimensional bonding interface. This dimensional expansion allows for increased bonding force and electrical connectivity without significantly increasing the overall footprint area of the device.
2Strength
If wafers are bonded with sufficient force for reliable electrical connectivity, then the bonding strength is improved, but delamination may occur during the bonding process
Solution Approach 1:
The bonding pad is segmented into two portions with different widths, allowing the bonding force to be distributed across different areas. The first portion with the first width and the second portion with the second width create multiple bonding interfaces, which distributes the bonding stress and reduces the risk of delamination while achieving sufficient overall bonding strength.
Solution Approach 2:
Different portions of the bonding pad have different local properties (different widths), allowing optimized bonding characteristics in each region. The first portion can be optimized for electrical connectivity while the second portion is optimized for mechanical bonding strength, achieving both goals simultaneously without causing delamination.
3Reliability
If the bonding via extends fully inside the bonding pad, then the electrical connectivity is maximized, but the bonding pad structure becomes complex and manufacturing becomes difficult
Solution Approach 1:
The bonding via extends partially inside the first portion of the bonding pad rather than fully through the entire bonding pad structure. This partial extension achieves sufficient electrical connectivity for reliable operation while simplifying the manufacturing process by reducing the complexity of via formation and alignment requirements compared to full extension designs.
Data Source
AI summary
A semiconductor device may include a peripheral circuit comprising a plurality of transistors, a cell array and a contact array positioned adjacent to each other over the peripheral circuit, a bonding pad for electrically connecting the peripheral circuit with the cell array and the contact array, the bonding pad comprising first and second portions, wherein the first portion has a first width and is in electrical connection with at least one transistor of the peripheral circuit, wherein the second portion has a second width that is less than the first width of the first portion, and wherein a bonding via electrically connecting the bonding pad with the contact array or the cell array extends partially inside the first portion of the bonding pad.