Memory Boot Acceleration with Predictive DFE Tap Validation

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Solution Overview

Problem

The boot process of memory devices, particularly in high-speed DRAMs like DDR4 and DDR5, is prolonged due to complex Decision Feedback Equalizer (DFE) training processes that mitigate inter-symbol interference, consuming significant time and resources.

Innovation Solution

A method and system utilizing a Decision Feedback Equalizer (DFE) training technique that predicts optimal DFE tap values using machine learning (ML) models based on configuration parameters, validates these values, and performs the boot process only when accuracy thresholds are met, thereby reducing the number of DFE trainings needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional DFE training is performed during boot process, then signal quality is improved, but boot time increases

Engineering Contradiction:
Improvesignal qualityVSAvoidboot time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing DFE tap values during system initialization or previous boot cycles. These pre-computed values are then reused during subsequent boot processes, eliminating the need for time-consuming real-time DFE training while maintaining signal quality improvement.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses copying by replicating successful DFE tap values from previous boot cycles or training sessions. Instead of performing complete DFE training anew each time, the system copies validated tap values from storage or memory, significantly reducing boot time while preserving the signal quality benefits of DFE training.

Inventive Principle:
Principle #26Copying

2Reliability

If comprehensive DFE training is performed, then interference removal is improved, but processing resources are consumed

Engineering Contradiction:
Improveinterference removalVSAvoidprocessing resources
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies partial action by performing only the necessary portion of DFE training - specifically, calculating and validating DFE tap values only when needed or using a reduced set of training data. This partial approach achieves sufficient interference removal while consuming fewer processing resources compared to comprehensive training.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent discards redundant training computations by storing and reusing previously validated DFE tap values. Instead of repeatedly performing complete DFE training, the system recovers and reuses successful tap values from previous operations, reducing processing resource consumption while maintaining interference removal effectiveness.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS20250343712A1Method and system for improving boot process of a memory using enhanced DFE training technique
Publication Date: 2025.11.06 SAMSUNG ELECTRONICS CO LTD
  • US20250343712A1 patent drawing
  • US20250343712A1 patent drawing
  • US20250343712A1 patent drawing

AI summary

Various example embodiments are directed to techniques for a booting process of a memory device using a Decision Feedback Equalizer (DFE) training technique. A method may include predicting one or more DFE tap values based on a plurality of configuration parameters of the memory device, determining an accuracy level of the predicted one or more DFE tap values based on a signal processed using the predicted one or more DFE tap values, and in response to the accuracy level of the predicted one or more DFE tap values being above an accuracy threshold value, setting a value of a prediction flag as TRUE, validating a plurality of eye margins of the signal processed using the predicted DFE tap values, storing the predicted DFE tap values based on results of the validation, and performing a subsequent boot process of the memory device using the predicted DFE tap values.