Memory Boot-Up Refresh for Short-Retention Cells
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Solution Overview
Problem
Existing semiconductor systems and memory devices face challenges in reducing the time taken to complete a boot-up operation, which affects user satisfaction.
Innovation Solution
A method of operation for memory devices that involves identifying and prioritizing memory cells with shorter data retention times, performing error correction and refresh operations on these cells, and adjusting reference voltages to ensure data within an error correction range, thereby optimizing boot-up efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction and refresh operations are performed on all memory cells during boot-up, then data reliability is improved, but boot-up time increases
Solution Approach 1:
The patent segments memory cells into two groups: first memory cells with shorter data retention times and second memory cells with longer data retention times. Error correction and refresh operations are selectively applied only to the first group during boot-up, rather than uniformly to all memory cells. This segmentation allows the system to maintain data reliability for critical cells while reducing overall boot-up time.
Solution Approach 2:
The patent applies different quality levels of error correction and refresh operations to different memory cell groups based on their specific retention characteristics. The first memory cells receive full error correction and refresh operations due to their shorter retention times, while the second memory cells with longer retention times receive reduced or no operations during boot-up, optimizing the balance between reliability and speed.
2Measurement precision
If reference voltage level is increased to reduce errors in memory cells, then data accuracy is improved, but power consumption increases
Solution Approach 1:
The patent adjusts the reference voltage level specifically for reading data from the first memory cells with shorter data retention times, rather than uniformly increasing voltage for all memory cells. This localized voltage adjustment targets the specific cells that require higher accuracy during boot-up, minimizing overall power consumption while maintaining data accuracy where it is most critical.
Solution Approach 2:
The patent dynamically changes the reference voltage parameter based on the specific requirements of different memory cell groups. By adjusting the reference voltage level selectively for the first memory cells during boot-up operations, the system optimizes the balance between data accuracy and power consumption, applying higher voltage only when and where necessary.
Data Source
AI summary
A method of operation of a memory device includes changing power from an off state to an on state, transmitting, to a controller, address information for memory cells having a shorter data retention time than other memory cells, reading data stored in memory cells corresponding the address information of the memory cells having the shorter data retention time and transmitting the data to the controller, and performing a refresh operation based on the results of an error correction operation of the controller.