Semiconductor Memory Boundary Circuit Area Reduction
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Solution Overview
Problem
Semiconductor memory devices, particularly NAND flash memory, face limitations in cell area and chip size due to the string structure of coupled cell transistors, which restricts data storage capacity and integration density.
Innovation Solution
A semiconductor memory apparatus with a boundary circuit unit that electrically couples low voltage and high voltage page buffers using integrated transistors and signal transmission lines, where the transistors are formed in isolated active regions and signal transmission lines are arranged in a bent shape to reduce the layout area and improve interconnection margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If signal transmission lines are arranged in a bent shape to reduce layout area, then the effective area of the page buffer is reduced, but the interconnection process margin is improved
Solution Approach 1:
The signal transmission line is configured in a bent shape instead of a straight line to reduce the layout area occupied by the page buffer. This curvature allows the line to fit within a smaller footprint while maintaining electrical connectivity, directly resolving the area reduction goal.
Solution Approach 2:
The signal transmission line transitions from a two-dimensional planar arrangement to a three-dimensional configuration by bending vertically or diagonally across multiple layers. This dimensional change allows the line to bypass the need for additional horizontal interconnection area while maintaining proper signal routing and process margins.
2Area of stationary object
If transistors are formed in isolated active regions, then the layout area is reduced, but the device complexity increases
Solution Approach 1:
The active region is divided into isolated sections where transistors are formed separately rather than in a continuous region. This segmentation allows for more efficient space utilization and reduced layout area while the standardized isolation techniques keep the manufacturing process manageable.
Solution Approach 2:
Isolated active regions are created only where transistors are needed, with non-active areas used for other purposes such as routing or passive devices. This localized approach to active region formation optimizes the layout area by eliminating unnecessary active region extensions while maintaining transistor performance.
3Area of stationary object
If additional interconnection areas are added, then the page buffer area increases, but the data storage capacity increases
Solution Approach 1:
The signal transmission line is merged with the bit line structure, allowing the same physical line to serve dual functions: transmitting signals within the page buffer and connecting to memory cell columns. This eliminates the need for separate interconnection areas and increases the area available for data storage.
Solution Approach 2:
The bent signal transmission line serves multiple functions: it acts as an interconnection within the page buffer, provides signal routing to multiple transistors, and connects to external bit lines. This multi-functionality reduces the total area required for interconnections while maintaining full data storage capacity.
Data Source
AI summary
A semiconductor memory apparatus includes a boundary circuit unit positioned between a low voltage page buffer and a high voltage page buffer and having circuits configured to electrically couple the low voltage page buffer and the high voltage page buffer. The boundary circuit unit includes: a first boundary circuit unit having first and second transistors configured to receive data of a corresponding memory cell area through a signal transmission line selected from a plurality of signal transmission lines extended and arranged along a first direction for each column; a second boundary circuit unit disposed adjacent in the first direction from the first boundary circuit unit and having the plurality of signal transmission lines extended and arranged thereon; and an active region where the first transistor is formed and an active region where the second transistor is formed are isolated from each other.