Memory Array Boundary Layout for CMP Edge Dishing Mitigation
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Solution Overview
Problem
In embedded memory systems, the planarization processes used in the metal gate replacement process can cause erosion and/or dishing along the edges of the memory devices, leading to control gates with smaller heights and increased leakage between the control gates and the semiconductor body.
Innovation Solution
An integrated chip design that includes a boundary region separating the embedded memory region from the logic region, featuring a memory wall and a logic wall. The logic wall is positioned above the memory wall and the memory devices, providing increased resistance to erosion and/or dishing during planarization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If planarization processes are used in metal gate replacement process, then manufacturing precision is improved, but erosion and dishing occur along edges of memory devices
Solution Approach 1:
A boundary region is introduced as an intermediary structure between the memory region and logic region. This boundary region includes a first dielectric material and a second dielectric material with different erosion rates, which mediates the interaction between the CMP process and the memory devices, preventing direct harmful effects on the memory device edges.
Solution Approach 2:
The boundary region is designed with spatially varying properties - the first dielectric material is positioned at memory device edges where erosion protection is most needed, while the second dielectric material is positioned in the logic region. This local differentiation allows targeted protection against erosion and dishing at critical locations.
2Object-affected harmful factors
If boundary region with different dielectric materials is introduced, then resistance to erosion and dishing is improved, but device complexity increases
Solution Approach 1:
The boundary region is segmented into distinct dielectric material regions - a first dielectric material adjacent to memory devices and a second dielectric material in the logic region. This segmentation allows each material to be optimized for its specific function while maintaining overall structural organization.
Solution Approach 2:
The boundary region with differentiated dielectric materials is formed in advance during the fabrication process, before the metal gate replacement process occurs. This preliminary structuring prevents erosion and dishing from the outset, avoiding the need for corrective actions later.
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of transistor devices disposed on or within a substrate. A plurality of memory devices are disposed on or within the substrate. A first isolation structure is disposed within the substrate between the plurality of transistor devices and the plurality of memory devices. The first isolation structure has a first upper surface and a second upper surface coupled to the first upper surface by a sidewall disposed therebetween. The first upper surface is vertically above the second upper surface. A dummy gate structure is arranged on the first upper surface.