Embedded Memory Boundary Sidewall Spacer for Etch Protection
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Solution Overview
Problem
The third etch process in integrated circuit (IC) manufacturing with embedded memory and high κ metal gate (HKMG) technology often damages the boundary sidewall, leading to lateral undercutting, divots, and trapping of high κ residue, which affects device performance and reliability by shifting doping profiles and contaminating process tools.
Innovation Solution
A method is introduced to form an IC with an embedded memory boundary structure that includes a boundary sidewall spacer, which protects the dummy sidewall from damage during the formation of logic devices, ensuring a smooth boundary and preventing high κ residue trapping, thereby enhancing yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the third etch process is performed to form logic devices, then the logic device structure is created, but the boundary sidewall is damaged causing lateral undercutting and divots
Solution Approach 1:
A boundary sidewall spacer is introduced as an intermediary protective layer between the etch process and the boundary sidewall. The spacer is formed conformally over the boundary isolation structure and dummy sidewall, then a portion is removed to create a protective barrier that prevents etch damage while allowing the etch process to proceed for logic device formation.
Solution Approach 2:
The boundary sidewall spacer is formed in advance before the third etch process. This preliminary protective structure is deposited conformally and then partially removed to expose specific areas while maintaining protection over the boundary sidewall, preventing damage before the harmful etch action occurs.
2Ease of manufacture
If the third etch process removes multilayer film and dummy capping layer, then logic region is exposed, but high κ residue is trapped in boundary sidewall damage
Solution Approach 1:
The boundary sidewall spacer acts as a protective intermediary that prevents etch-induced damage and residue trapping. By maintaining a smooth, protected boundary sidewall during the etch process, the spacer prevents the formation of divots and lateral undercutting where high κ residue could become trapped.
Solution Approach 2:
The boundary sidewall spacer provides preliminary protection against the harmful effects of the etch process. By being in place before the etch occurs, it prevents the creation of surface irregularities that would otherwise trap residue, thereby preventing a future problem before it arises.
3Ease of operation
If boundary sidewall is damaged, then etch access is improved, but doping profile shifts and process tool contamination occur
Solution Approach 1:
The boundary sidewall spacer serves as a protective mediator that allows the etch process to proceed effectively while preventing damage to the boundary sidewall. This maintains the integrity needed for stable doping profiles and prevents contamination that would compromise device reliability.
Data Source
AI summary
Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.