Memory Compiler Breakpoint Identification via Signal Slope Analysis

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Solution Overview

Problem

Existing memory compilers face challenges in efficiently identifying breakpoints for memory arrays, leading to increased simulation overhead and reduced productivity in memory design and tuning.

Innovation Solution

A method and apparatus for memory processing that determine read signals for different column quantities per section of a memory, calculate differences between these signals, and identify breakpoints to generate a memory representation, thereby reducing the number of simulations required.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional memory compiler methods are used to identify breakpoints, then comprehensive memory analysis is achieved, but simulation overhead increases and productivity decreases

Engineering Contradiction:
Improvebreakpoint identification accuracyVSAvoidmemory design efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The memory array is divided into multiple sections, and breakpoints are identified independently for each section rather than analyzing the entire memory array as a single unit. This segmentation reduces the complexity and simulation overhead while maintaining accurate breakpoint identification for each segment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The method performs preliminary calculations of bitline signal slopes and read signals before conducting full simulations. By pre-determining breakpoints based on calculated slopes and signal differences, the approach reduces the number of required simulations and accelerates the memory design process.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If detailed analysis of all memory sections is performed, then accurate memory representation is generated, but the number of simulations required increases

Engineering Contradiction:
Improvememory representation accuracyVSAvoidsimulation time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The memory array is divided into multiple sections, and breakpoints are identified independently for each section rather than analyzing the entire memory array as a single unit. This segmentation reduces the complexity and simulation overhead while maintaining accurate breakpoint identification for each segment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The method performs partial analysis by calculating slopes and read signals for different column quantities per section, identifying breakpoints only where necessary based on signal differences. This partial action approach generates accurate memory representations without requiring exhaustive simulation of all memory sections.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250078916A1Techniques for identifying self-time and breakpoints for memory
Publication Date: 2025.03.06 SYNOPSYS INC
  • US20250078916A1 patent drawing
  • US20250078916A1 patent drawing
  • US20250078916A1 patent drawing

AI summary

Certain aspects of the present disclosure include a method for memory processing. The method generally includes determining, via one or more processors and for each of different quantities of columns per section of a memory, a read signal indicating a change in a bitline signal during a read window based on at least one calculated slope of the bitline signal during the read window, where the read signal being determined for each of the different quantities of the columns per section of the memory yields a plurality of read signals; determining a difference between at least two of the plurality of read signals, identifying breakpoints within the memory based on the difference between the at least two of the plurality of read signals. The method also includes generating a representation of the memory based on the breakpoints.