Universal Memory Bridge Chip TSV Interface Compatibility
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Solution Overview
Problem
In electronic devices, the stacking and packaging of semiconductor chips with different interfaces using Through Silicon Via (TSV) methods require multiple TSVs, leading to reduced design area and increased process costs due to potential chip damage and complex interface management.
Innovation Solution
A semiconductor device employing a universal memory bridge chip with TSVs to electrically connect chips with different interfaces, allowing for efficient signal exchange and reducing the need for multiple TSVs by providing a compatible interface, thereby increasing design area and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple TSVs are used to connect semiconductor chips with different interfaces, then electrical connection and interface compatibility are achieved, but design area reduction and process costs increase
Solution Approach 1:
The patent applies universality by designing a standardized TSV interface structure that can accommodate multiple different chip interfaces through a common penetration architecture. The memory device and processor chip both use the same TSV penetration method, allowing different interface types to be connected through a universal structural framework, thus achieving interface compatibility without requiring separate penetration structures for each interface type.
Solution Approach 2:
The patent uses the TSV structure as an intermediary element that mediates the connection between chips with different interfaces. The TSV penetration structure acts as a mediator layer that translates and connects different interface types through a standardized vertical penetration path, enabling electrical connection between dissimilar interfaces while maintaining a consistent design area footprint.
2Reliability
If multiple TSVs are used to penetrate semiconductor chips, then electrical connection between chips is achieved, but process costs increase due to potential chip damage
Solution Approach 1:
The patent applies segmentation by dividing the TSV penetration process into distinct stages: forming TSV holes through the substrate, depositing conductive materials in segments, and selectively connecting different chip interfaces. This segmented approach allows for controlled manufacturing where each TSV can be independently formed and tested, reducing the risk of catastrophic chip damage and enabling rework or replacement of individual TSVs without compromising the entire chip structure.
3Volume of moving object
If chip stacking is implemented to minimize internal space, then volume reduction is achieved, but design area reduction occurs due to TSV penetration space requirements
Solution Approach 1:
The patent applies dimensionality change by transitioning from a two-dimensional planar layout to a three-dimensional stacked architecture. Multiple chips are arranged vertically along the Z-axis, with TSVs providing vertical interconnects through the stack. This vertical stacking in the third dimension dramatically reduces the horizontal footprint and overall device volume, while the TSV penetration structures are designed to minimize lateral space occupation, thus achieving volume reduction without significant design area penalty.
Data Source
AI summary
An electronic device includes: a communication module; an input module; a display; an interface; at least one sensor; a memory; and a processor module. The processor module includes at least one of: at least one dummy chip including at least one Through Silicon Via (TSV); at least one memory bridge including at least one TSV; at least one memory connected to the at least one dummy chip and the at least one memory bridge and that can exchange an electric signal through the at least one dummy chip and the at least one memory bridge; or at least one processor. The at least one processor may be configured to exchange an electric signal through the at least one memory bridge, and to transmit an electric signal to at least one of the communication module, input module, display, interface, at least one sensor, or first memory. The at least one processor may exchange information via a circuit path that includes at least one of the memory bridge and a portion of the at least one memory, when transmitting the electric signal.