Memory Controller Write Buffer for Dynamic Burst Page Writes
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Solution Overview
Problem
Existing memory controllers face challenges in achieving improved write performance for non-volatile memories due to fixed burst write lengths that do not optimize based on buffer contents, leading to inefficiencies and increased latency.
Innovation Solution
A memory controller with a read/write buffer that allows for burst writes of arbitrary length, determined by the contents of the buffer, optimizing write operations by ensuring consecutive page addresses are accessed, thereby reducing row switching and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fixed burst write lengths are used in memory controllers, then device complexity is reduced and control is simplified, but write performance is not optimized and latency increases
Solution Approach 1:
The patent implements dynamic burst write length adjustment where the memory controller adapts the burst write length based on the actual number of valid data entries in the write buffer. Instead of using fixed predetermined lengths, the system dynamically determines optimal burst lengths by monitoring buffer contents, thereby maximizing write throughput without requiring complex external control mechanisms.
Solution Approach 2:
The memory controller autonomously manages buffer contents and self-determines optimal burst write lengths by monitoring its own buffer state. The controller automatically identifies consecutive page addresses in the buffer and initiates burst writes without external intervention, eliminating the need for complex external coordination while maintaining optimized performance.
2Loss of time
If arbitrary length burst writes are implemented based on buffer contents, then write efficiency is improved and row switching is minimized, but control complexity increases
Solution Approach 1:
The patent prepares data in the write buffer in advance with organized page addresses before initiating burst writes. By pre-loading consecutive pages into the buffer and organizing them by address sequence, the system enables immediate burst writes without waiting for data assembly, thereby reducing write latency while keeping control logic relatively simple.
Solution Approach 2:
The memory controller continuously monitors the write buffer contents and uses this feedback to dynamically determine burst write lengths. The controller checks for consecutive page addresses in the buffer and adjusts burst parameters based on real-time buffer state, optimizing write timing without requiring complex external control mechanisms.
3Productivity
If consecutive page addresses are accessed in burst writes, then row switching is reduced and performance improves, but buffer management becomes more complex
Solution Approach 1:
The patent applies local quality optimization by organizing buffer entries according to their page address characteristics. The buffer structure prioritizes storage and retrieval of consecutive page addresses, creating locally optimized address sequences that enable efficient burst writes to consecutive pages while maintaining overall buffer management simplicity.
Data Source
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AI summary
A non-volatile memory (NVM) controller is configured to control reads from and writes to an NVM array, and includes a write buffer and a buffer control circuit. The write buffer includes a plurality of entries, each configured to store a write access having a corresponding page address of the NVM array and corresponding write data. The buffer control circuit is configured to store a write access having a corresponding page address of the NVM array and corresponding write data, and generate burst writes from the write buffer to the NVM array. The buffer control circuit generates a burst write by sequentially selecting write accesses from the write buffer which have consecutive page addresses, in which the length of the burst write is undefined when the burst write to the NVM array is initiated.