Memory Buffer Voltage Timing Calibration via Controller Extraction
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Solution Overview
Problem
Existing memory systems require complex and costly hardware designs for voltage and timing calibration due to the need for dedicated micro-processors in memory buffers, leading to increased costs and prolonged development cycles.
Innovation Solution
A method for voltage and timing calibration in memory systems where the memory controller adjusts its timing and voltage based on feedback from the memory buffer, and subsequently adjusts the read/write timing and voltage of memory chip units, reducing the need for a signal generation unit in the memory buffer and simplifying the buffer's circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dedicated micro-processor is disposed in the memory buffer to generate control instructions for calibration, then the calibration function can be implemented, but the device complexity and cost increase significantly
Solution Approach 1:
The patent extracts the signal generation unit from the memory buffer and relocates it to the memory controller. This separation removes the complex micro-processor requirement from the memory buffer, simplifying the buffer's circuit design while maintaining the calibration function through the memory controller's existing resources.
Solution Approach 2:
The memory controller is enhanced to perform multiple functions: it not only controls normal memory operations but also generates all necessary control instructions, timing signals, and voltage calibration signals for the memory buffer and memory chips. This multi-functionality eliminates the need for dedicated calibration hardware in the buffer.
2Extent of automation
If pure hardware is used for calibration signal generation in the memory buffer, then the calibration can be performed, but the circuit design becomes complicated and development time increases
Solution Approach 1:
The patent extracts the signal generation capability from the memory buffer's hardware and consolidates it in the memory controller. This allows the buffer to maintain simple hardware architecture while the controller provides the necessary automated calibration signal generation through its existing control logic.
3Adaptability or versatility
If a dedicated micro-processor is added to the memory buffer for calibration, then the calibration function is achieved, but the manufacturing cost increases greatly
Solution Approach 1:
The patent removes the expensive micro-processor component from the memory buffer by extracting the signal generation function and relocating it to the memory controller. This eliminates the need for additional high-cost components in the buffer, significantly reducing manufacturing costs while preserving calibration capability.
4Manufacturing precision
If calibration is performed by adjusting timing and voltage at both memory controller side and memory chip side independently, then accurate calibration is achieved, but the calibration process becomes complex and time-consuming
Solution Approach 1:
The patent merges the calibration control functions into a single coordinated process managed by the memory controller. The controller generates unified control instructions that simultaneously adjust timing and voltage parameters at both the memory buffer and memory chip sides, achieving accurate calibration through integrated control rather than independent adjustments.
Solution Approach 2:
The patent implements a feedback mechanism where the memory controller receives data from the memory buffer and memory chips, processes this feedback information, and adjusts the calibration parameters accordingly. This iterative feedback process enables precise timing and voltage calibration while simplifying the overall control logic through automated adjustment based on actual performance data.
Data Source
AI summary
A voltage and timing calibration method used in a memory system. A memory controller adjusts timing and voltages of the controller and voltages of a memory buffer according to data returned by the buffer based on timing and voltages at a memory controller side of the buffer, to calibrate timing and voltages between the controller and controller side. According to data read by the buffer from a memory chip unit on the basis of timing and voltages at a memory chip side of the buffer, the controller adjusts the timing and voltage at the chip side and the voltage of the chip unit; or the buffer adjusts the timing and voltage at the chip side and the voltage of the chip unit, to calibrate the timing and voltage between the chip side and chip unit. Therefore, hardware resources of the buffer can be saved and the circuit can be simplified.