Memory Buffer Chip Asynchronous Command Management
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Solution Overview
Problem
Conventional memory systems face design complexity due to differences in operating frequencies between memory controllers and memory chips, particularly when high capacity or multiple ranks are involved, leading to speed degradation and increased design difficulty.
Innovation Solution
A memory system that operates in an asynchronous manner, utilizing a memory buffer chip with a command generation unit, data buffer, register, and control unit to manage command credits and timing parameters, allowing for efficient command and data transmission regardless of operating speeds, and includes a timing management unit to prevent data conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If synchronous interface technology is used to simplify design, then design complexity is reduced, but operating frequency differences between memory controller and memory chips cause timing issues and speed degradation
Solution Approach 1:
The patent introduces a buffer chip as an intermediary component between the memory controller and memory chips. This buffer chip includes a command buffer that stores commands and a timing management unit that handles timing parameters, acting as a mediator that decouples the synchronous interface from the actual memory operations, thereby resolving timing issues while maintaining design simplicity
Solution Approach 2:
The command buffer in the buffer chip stores commands in advance before they are executed by the memory chips. This preliminary storage of commands allows the timing management unit to prepare and adjust timing parameters ahead of time, ensuring accurate timing even when operating frequencies differ between components
2Quantity of substance
If high capacity is implemented by coupling multiple ranks to one channel, then memory capacity is increased, but operating frequency differences cause speed degradation
Solution Approach 1:
The buffer chip serves as an intermediary that manages commands for multiple ranks coupled to one channel. The command buffer stores and manages commands for different ranks, while the timing management unit adjusts timing parameters specifically for multi-rank operations, maintaining high operating speeds despite the increased capacity
Solution Approach 2:
The timing management unit dynamically adjusts timing parameters based on the specific rank being accessed and the current operating conditions. This dynamic adjustment allows the system to maintain optimal speed when accessing multiple ranks with potentially different operating characteristics
3Use of energy by moving object
If memory chips with low operating frequency are used for yield or low power consumption, then power consumption is reduced, but frequency differences between controller and chips increase design difficulty
Solution Approach 1:
The buffer chip acts as an intermediary that absorbs the frequency difference between the high-speed memory controller and low-speed memory chips. The command buffer and timing management unit handle the frequency translation and timing adjustment, allowing the use of low-frequency chips for power efficiency without increasing controller design complexity
Solution Approach 2:
The patent extracts the frequency matching and timing management functionality from the memory controller and places it in the separate buffer chip. This extraction allows the controller to operate at high speed while the buffer chip handles the frequency adaptation to low-speed chips, reducing the controller's design burden
Data Source
AI summary
A memory system may be provided. The memory system may include a memory buffer chip coupled to one or more memory chips. The memory system may include a memory controller configured to control the memory buffer chip to input/output data to/from the one or two or more memory chips. The memory buffer chip may include a first interface configured to transmit/receive a signal to/from the memory controller. The memory buffer chip may include a second interface configured to transmit/receive a signal to/from the memory chip. The memory buffer chip may include a command buffer configured to buffer commands received from the memory controller through the first interface. The memory buffer chip may include a read buffer configured to buffer read data received from the memory chip.