Fine-Grained Memory Buffer Access Tracking via Counter Pairs

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Solution Overview

Problem

High performance computing (HPC) systems face challenges in determining the completion status of remote memory access operations, leading to delays in identifying stabilized memory regions due to the lag between locally managed offsets and completion counters, especially with unordered messages and retransmissions.

Innovation Solution

Implementing a system that uses multiple counter pairs with a locally managed offset and a completion counter for each request, allowing for fine-grained tracking of memory buffer accesses, and a stable pointer to indicate regions no longer in use, with dedicated counter logic unit for efficient management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a single completion counter is used to track remote memory access operations, then the system structure remains simple, but it becomes impossible to determine which specific regions of the memory buffer have stabilized when multiple operations are pending

Engineering Contradiction:
Improvecompletion status tracking precisionVSAvoidcounter management complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the single completion counter into multiple completion counters, with each counter pair (LMO and CC) tracking a specific region or operation independently. This segmentation allows precise determination of which memory buffer regions have stabilized while maintaining manageable complexity through structured organization of counter pairs.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the locally managed offset advances continuously to accommodate new remote access requests, then the system supports high throughput and concurrency, but the completion counter continually lags behind, causing long delays in identifying stabilized memory regions

Engineering Contradiction:
Improveremote access throughputVSAvoidstabilization detection delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

By segmenting the memory buffer tracking into multiple independent counter pairs, the system allows the LMO to advance continuously for new requests while individual CCs track completion for specific regions. This enables parallel tracking of multiple operations, reducing the time delay in identifying stabilized regions while maintaining high throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements feedback mechanisms where completion status is continuously monitored and used to update the stable pointer. When a CC catches up to its corresponding LMO, this feedback triggers identification of stabilized memory regions, allowing the system to respond dynamically to completion events without delaying throughput operations.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If multiple counter pairs are implemented for fine-grained tracking, then stabilization detection accuracy improves, but the device complexity and resource requirements increase

Engineering Contradiction:
Improvestabilization detection accuracyVSAvoidcounter pair management complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the tracking function into multiple counter pairs, each responsible for a specific region or operation, thereby achieving fine-grained stabilization detection accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each counter pair is designed as a universal module that can track any remote memory access operation independently. This multi-functionality allows the same counter pair structure to handle diverse operations, reducing overall system complexity through reuse of standardized components while maintaining precise tracking capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10963183B2Technologies for fine-grained completion tracking of memory buffer accesses
Publication Date: 2021.03.30 INTEL CORP
  • US10963183B2 patent drawing
  • US10963183B2 patent drawing
  • US10963183B2 patent drawing

AI summary

Technologies for fine-grained completion tracking of memory buffer accesses include a compute device. The compute device is to establish multiple counter pairs for a memory buffer. Each counter pair includes a locally managed offset and a completion counter. The compute device is also to receive a request from a remote compute device to access the memory buffer, assign one of the counter pairs to the request, advance the locally managed offset of the assigned counter pair by the amount of data to be read or written, and advance the completion counter of the assigned counter pair as the data is read from or written to the memory buffer. Other embodiments are also described and claimed.