Memory Controller Buffer Logic for NAND Cell Coupling Errors
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Solution Overview
Problem
High-density recording in nonvolatile memory devices leads to increased capacitive coupling between neighboring memory cells, causing data garbling and irrecoverable errors, even with high error correcting codes, due to the proximity of memory cells in NAND flash memory.
Innovation Solution
A memory device with a data pattern check circuit and a data correction circuit that temporarily stores data in a buffer, checks for predetermined data patterns, and corrects or inverts data values before writing to prevent garbling by adjusting the data pattern, thereby enhancing reliability and reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-density recording is implemented to increase memory capacity, then memory capacity increases, but data garbling occurs due to increased capacitive coupling between neighboring memory cells
Solution Approach 1:
The patent applies preliminary action by checking data patterns before writing them to memory. The data pattern check circuit identifies patterns that would cause garbling due to capacitive coupling, and the data correction circuit pre-corrects these patterns by inverting affected data values. This preventive correction before writing eliminates the reliability issue while maintaining high-density recording capability.
Solution Approach 2:
The patent applies preliminary anti-action by anticipating the harmful effect of capacitive coupling and counteracting it in advance. The system identifies data patterns that would be affected by neighboring cell interference and inverts the data values at positions that would otherwise be garbled. This pre-applied counter-action ensures that even when capacitive coupling occurs during high-density recording, the data remains reliable.
2Reliability
If error correcting codes with high error correcting capability are used, then error correction capability improves, but data garbling due to capacitive coupling remains irrecoverable
Solution Approach 1:
The patent applies preliminary action by performing data pattern checking and correction before writing data to memory, rather than relying solely on post-read error correction. The data pattern check circuit identifies patterns that would cause garbling, and the data correction circuit pre-corrects them by inverting data values at positions susceptible to capacitive coupling. This prevents the information loss that would otherwise require complex error correcting codes to recover.
3Productivity
If data is written directly to memory cells without correction, then writing speed is fast, but data garbling occurs in neighboring memory cells
Solution Approach 1:
The patent applies preliminary action by implementing a data pattern check circuit and data correction circuit that operate before data is written to memory. These circuits identify and correct patterns that would cause garbling due to capacitive coupling, ensuring data accuracy is maintained without significantly impacting writing speed. The correction process is integrated into the write path, allowing fast writing while preventing data garbling in neighboring cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents data garbling, improves reliability, and allows for higher integration density and reduced correction positions, enhancing decoding performance by addressing capacitive coupling issues in high-density memory devices.
Implementation Method 1
the value of capacitive coupling occurring between the floating gates (FG) of neighboring memory cells increases
Data Source
AI summary
A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory.