Advanced Memory Buffer Delay Calibration for Phase-Aligned DRAM Buses
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Solution Overview
Problem
Conventional memory systems using un-buffered or registered DIMMs connected via a stub bus experience performance degradation as the number of modules increases, limiting the performance of dynamic random access memory (DRAM) systems. Fully Buffered Dual In-line Memory Module (FB-DIMM) technology addresses this by employing high-speed, serial, point-to-point connections, but it faces challenges in calibrating read/write operations across data buses of varying lengths due to trace differences and receiver mismatches.
Innovation Solution
An advanced memory buffer (AMB) with adjustable circuits and a calibration controller is used to level delays on point-to-point data buses, ensuring phase alignment of data signals across different buses, thereby reducing phase differences and increasing time margin and jitter tolerance during read/write operations. This involves adjustable delay blocks and a calibration phase where a common data pattern is written and read to adjust delays, ensuring correct write and read operations across multiple data buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If point-to-point connections are used to increase memory system performance, then channel performance is improved, but phase differences across data buses of varying lengths cause errors and reduced system performance
Solution Approach 1:
The patent applies preliminary action by performing delay calibration before normal memory operations. The calibration controller adjusts the delay blocks during an initial calibration phase to pre-compensate for phase differences, ensuring that data arrives at the correct timing during subsequent read/write operations, thereby preventing errors before they occur
Solution Approach 2:
The patent changes the delay parameter of each data bus dynamically during calibration. The calibration controller measures phase differences and adjusts the delay block parameters to equalize arrival times across all data buses, transforming the system from having fixed, varying delays to having compensated, equalized delays, thus resolving the phase alignment issue
2Quantity of substance
If data buses of different lengths are used in point-to-point connections, then memory capacity and bandwidth are increased, but phase alignment errors occur
Solution Approach 1:
The patent introduces delay blocks as intermediary components in the data path between the memory controller and memory modules. These delay blocks act as mediators that can be adjusted to compensate for the inherent phase differences caused by varying data bus lengths, allowing the system to maintain phase alignment despite using data buses of different lengths to achieve higher memory capacity
Solution Approach 2:
The calibration process performs preliminary measurement and adjustment of delay blocks before normal operation. During this initial phase, the calibration controller determines the appropriate delay values for each data bus based on their lengths, pre-configuring the system to handle phase alignment correctly during subsequent high-capacity memory operations
Data Source
AI summary
Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data buses; a port to interface with a common clock bus for the plurality of data buses; and an adjustable circuit coupled with the plurality of ports to level delays on the plurality of data buses. In one embodiment, the data buses have different wire lengths between the dynamic random access memory (DRAM) memory chips and the advanced memory buffer (AMB).