Memory Module Buffer With Graduated On-Die Termination
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Solution Overview
Problem
High-speed signaling systems with single on-die termination schemes experience sub-optimal performance due to impedance discontinuity and signal attenuation, leading to reduced signaling margins and increased error rates.
Innovation Solution
Implementing multiple, graduated on-die termination structures per high-speed signaling line, allowing for switchable selection between high-load and low-load terminations based on whether the memory module is the destination for incoming signals, thereby optimizing impedance matching and energy absorption without undue signal attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single on-die termination structure is used, then device complexity is reduced, but signaling performance deteriorates due to impedance discontinuity and signal attenuation
Solution Approach 1:
The patent divides the termination structure into multiple segmented termination circuits (first termination circuit and second termination circuit) with different termination impedance values. This segmentation allows selective activation of appropriate termination circuits based on signal direction, resolving the contradiction by providing both simplified overall structure and optimized local termination performance.
Solution Approach 2:
The patent implements dynamic termination by using switch elements that can dynamically connect or disconnect different termination circuits based on whether the memory module is the destination or source of data signals. This dynamic adaptation optimizes signaling performance for different operational states while maintaining manageable device complexity.
2Object-generated harmful factors
If on-die termination is asserted at selected memory module, then reflections are suppressed, but signal attenuation increases reducing signaling margin
Solution Approach 1:
The patent applies different termination impedance values at different locations (first termination circuit with first impedance value, second termination circuit with second impedance value) based on the local requirement. The selected memory module uses a termination circuit with impedance optimized for its specific role, suppressing reflections locally without excessive attenuation.
Solution Approach 2:
The patent changes the termination impedance parameter based on operational state by selecting between different termination circuits with different impedance values. This parameter adaptation allows optimization of both reflection suppression and signal attenuation for each specific operational condition.
3Loss of energy
If on-die termination is deasserted at selected memory module, then signal attenuation is reduced, but impedance discontinuity increases causing sub-optimal signaling
Solution Approach 1:
The patent dynamically adjusts the termination state by selectively connecting or disconnecting different termination circuits based on whether the memory module is the destination. This dynamic control maintains impedance continuity when needed while reducing attenuation when the module is the source.
Solution Approach 2:
The memory module is designed with multi-functional termination capability, able to serve both as destination (with termination asserted) and source (with termination deasserted) of data signals. This universality allows the same module to optimize for different operational roles, maintaining both impedance continuity and low attenuation as needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signaling margins, reduces bit error rates, and provides additional headroom for increased signaling rates by effectively managing reflections and signal transmission.
Implementation Method 1
terminating elements have been implemented by discrete resistors connected to metal traces on a mother board or other printed circuit board
Data Source
AI summary
In memory module having multiple data inputs to couple to signal lines of an external data path, multiple memory integrated-circuits (ICs) and a buffer IC, the buffer IC includes respective interfaces coupled to the data inputs and the memory ICs, a first termination circuit having a first load element and a first switch element to switchably couple the first load element to a first data input of the data inputs and a second termination circuit having a second load element and a second switch element to switchably couple the second load element to the first data input. The buffer IC further includes a configuration circuit to store, in response to control information from a memory controller, a first digital value and a second digital value, the first digital value being supplied to the first termination circuit to control an impedance of the first load element and the second digital value being supplied to the second termination circuit to control an impedance of the second load element.