Memory Buffer ECC for Multi-Error Correction in DRAM Modules
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Solution Overview
Problem
Conventional memory systems struggle to effectively correct multi-errors in memory storage devices that are increasingly susceptible to interference due to shrinking storage cells, requiring significant changes to host controllers and system infrastructure, which negatively impact access latency and storage overhead.
Innovation Solution
A memory module with a memory buffer and an integrated error detection and correction circuit that computes and stores parity bits in parallel with data words, enabling detection and correction of single and multi-errors, and using data steering methods to direct data around faulty storage cells to redundant RAM chips or SRAM within the buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error detection and correction methods are used in host controllers, then single errors can be detected and corrected, but multi-errors cannot be corrected and access latency increases
Solution Approach 1:
The error detection and correction circuit is extracted from the host controller and placed within the memory module itself. This allows the memory module to independently handle error correction for both single and multi-errors without burdening the host controller, thereby maintaining low access latency while improving reliability.
Solution Approach 2:
A memory buffer is introduced as an intermediary component within the memory module, positioned between the RAM chips and the host controller. This buffer contains the error detection and correction circuit, serving as a mediator that processes data before it reaches the host controller, enabling sophisticated error correction without impacting system performance.
2Reliability
If multi-error correction is implemented in host controllers, then reliability improves, but system complexity and infrastructure changes are required
Solution Approach 1:
The complex multi-error correction functionality is extracted from the host controller and relocated to the memory module. This extraction eliminates the need for complex host controller modifications while maintaining advanced error correction capabilities, as the memory module self-manages its error correction operations.
Solution Approach 2:
The error detection and correction circuit is merged with the memory buffer within the memory module, creating an integrated solution. This combination allows the memory module to handle both error detection and correction functions locally, eliminating the need for separate host controller infrastructure and reducing overall system complexity.
3Quantity of substance
If storage cells are shrunk to increase density, then storage capacity improves, but susceptibility to interference and errors increases
Solution Approach 1:
The error detection and correction circuit provides beforehand cushioning by proactively detecting and correcting errors before they propagate through the system. This protective mechanism is especially important for shrunk storage cells that are more susceptible to interference, as it compensates for the increased error probability without requiring larger cell sizes.
Solution Approach 2:
The invention uses additional parity bits and correction codes as disposable information elements that can be easily generated and processed. These extra data elements act as a protective layer over the shrunk storage cells, allowing the system to tolerate higher error rates inherent in high-density storage without compromising overall reliability.
Data Source
AI summary
The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another.