Memory Buffer Segmentation for EDC Coverage
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Solution Overview
Problem
Existing memory systems lack efficient error detection and correction capabilities without modifying the existing non-EDC memory controllers, which limits their ability to handle errors effectively during data access transactions.
Innovation Solution
A memory buffer is introduced that decodes primary memory addresses into secondary addresses to access data and error information from separate groups of memory devices, enabling error detection and correction operations without widening the data bus or adding extra memory devices, and allowing for configurable EDC coverage based on specific needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If EDC capabilities are added to memory systems by widening the data bus or adding extra memory devices, then error detection and correction capability is improved, but device complexity and bandwidth utilization are worsened
Solution Approach 1:
The patent segments the memory system into two distinct groups: data storage devices and error information storage devices. This segmentation allows EDC functionality to be implemented without requiring a wider data bus, as error information is accessed separately from data. The memory controller independently manages data accesses and error information accesses, enabling full bandwidth utilization while providing EDC coverage.
Solution Approach 2:
The patent introduces an intermediary mechanism where error information is stored in separate memory devices and accessed through separate command sequences. This intermediary approach allows the system to detect and correct errors without directly embedding error information in the data path, thus avoiding data bus widening and maintaining full bandwidth while improving reliability.
2Reliability
If EDC capabilities are added to memory systems, then error detection and correction capability is improved, but power consumption is worsened
Solution Approach 1:
The patent implements periodic action by only accessing error information when specifically needed for EDC operations, rather than continuously monitoring all data. The memory controller selectively initiates error information access based on data access patterns and EDC requirements, reducing unnecessary power consumption while maintaining error detection and correction capability when required.
3Reliability
If EDC capabilities are added to memory systems with modification to existing controllers, then error detection and correction capability is improved, but ease of manufacture is worsened
Solution Approach 1:
The patent implements universality by designing the memory controller to handle both data accesses and error information accesses through a unified command interface. The controller can operate in different modes (data-only access, EDC-enabled access) without requiring hardware modifications, making the solution easily manufacturable while providing EDC capability. The same controller infrastructure serves multiple functions: data storage, error information storage, and EDC operations.
Data Source
AI summary
A memory system supporting error detection and correction (EDC) coverage. The system includes a memory controller and a memory buffer. The memory buffer includes an interface to a first group of memory devices and an interface to a second group of memory devices. The memory buffer accesses data from the first group of memory devices and accesses first error information corresponding to the data from the second group of devices. The memory buffer also accesses additional data from the second group of memory devices and accesses second error information corresponding to the additional data from a device in the first group of memory devices. EDC coverage may also be configured by the memory controller so that some data accesses have EDC coverage and other data accesses do not have EDC coverage.