Memory Buffer Error Tracking for Multi-Bit Failure Repair
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Solution Overview
Problem
Memory systems employing error codes face limitations in correcting multiple-bit errors, leading to premature failure of memory components when multiple hard errors occur, especially during assembly and testing of memory modules.
Innovation Solution
Incorporating a buffer circuit with error logic and repair logic within the memory module to identify and repair storage cell failures, allowing for transparent error correction and maintaining the error correction capability of the memory controller, thereby preventing recurring hard errors and extending the error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If error codes with redundancy are employed to detect and correct errors, then single-bit error correction capability is improved, but the ability to correct multiple-bit errors deteriorates
Solution Approach 1:
The patent segments the error correction function into two independent parts: (1) error detection code in the memory device that identifies single-bit errors, and (2) error tracking and repair logic in the buffer that detects and repairs hard errors by remapping defective storage cells to spare cells. This segmentation allows each part to be optimized independently, enabling the system to correct multiple-bit errors while maintaining single-bit error detection capability.
Solution Approach 2:
The buffer acts as an intermediary component between the memory device and the memory controller. It introduces error tracking and repair logic that monitors errors from the error detection code and performs repairs before data reaches the controller. This intermediary function extends the error correction capability without requiring changes to the memory controller design.
2Reliability
If error correction codes are used in memory systems, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent divides the error correction functionality into separate components: error detection code in the memory device, error tracking logic in the buffer, and repair logic in the buffer. This segmentation distributes complexity across different components rather than concentrating it in one place, making the overall system more manageable and maintainable.
Solution Approach 2:
The error tracking and repair logic in the buffer operates autonomously to detect hard errors and perform repairs without requiring external intervention from the memory controller or host system. The buffer self-manages the error correction process by monitoring error codes, identifying defective cells, and remapping data to spare cells, thereby reducing the complexity burden on other system components.
3Ease of manufacture
If hard errors are allowed to occur in memory devices, then manufacturing yield is improved, but system reliability deteriorates due to premature failure
Solution Approach 1:
The patent implements preliminary error tracking and repair functionality in the buffer that proactively identifies and repairs hard errors before they cause system failure. The error tracking logic continuously monitors for hard errors using error codes, and the repair logic automatically remaps defective storage cells to spare cells, preventing error accumulation that would lead to premature failure. This preliminary action allows memory devices to be manufactured with acceptable yield while maintaining long-term reliability.
Data Source
AI summary
A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.