Memory Device Buffering Fail Data for Testing Efficiency
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Solution Overview
Problem
Conventional memory device testing methods are inefficient, requiring lengthy test times and excessive use of input/output resources due to the need to read and compare data from both passing and failing memory cells, which limits manufacturing productivity and increases costs.
Innovation Solution
Implementing a method where only fail data is stored and conveyed to a tester, without address data associated with passing memory cells, using a buffer to process and store fail data, and optimizing data transfer to reduce the amount of data transferred and resources used during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods read and compare data from both passing and failing memory cells, then complete test coverage is achieved, but testing time and I/O resource usage increase significantly
Solution Approach 1:
The patent extracts only the relevant information (fail data) from the complete test data set, eliminating the need to process and transfer pass data. The buffer stores only fail data identifiers, and the I/O circuit transfers only this extracted information to the tester, resolving the contradiction between complete test coverage and reduced testing time.
Solution Approach 2:
Instead of the conventional approach of reporting all test results (pass and fail), the patent inverts the reporting mechanism to report only failures. This inversion fundamentally changes the data flow from comprehensive reporting to selective failure reporting, achieving both complete test coverage and reduced I/O usage.
2Loss of information
If conventional testing methods transfer all test data to the tester, then complete test information is available, but I/O resource usage and data transfer volume increase
Solution Approach 1:
The patent extracts only the essential failure information from the complete test data set. The buffer stores identifiers for failing memory cells, and only this extracted fail data is transferred to the tester via the I/O circuit, dramatically reducing data transfer volume while preserving all necessary test information for quality control.
Solution Approach 2:
The patent inverts the conventional data transfer approach by transferring only failure information rather than all test data. This inversion reduces the quantity of data transferred while ensuring that all critical test information (failures) is preserved for analysis.
3Reliability
If conventional testing methods process all memory cell data, then comprehensive quality control is achieved, but manufacturing productivity decreases
Solution Approach 1:
The patent extracts only fail data from the complete test results, storing identifiers in the buffer and transferring only this extracted information to the tester. This extraction approach maintains comprehensive quality control by capturing all failures while dramatically improving manufacturing productivity by reducing processing and transfer time.
Solution Approach 2:
The patent inverts the conventional approach of processing all test data by instead processing only failure data. This inversion maintains quality control by ensuring all failures are captured and reported, while simultaneously improving manufacturing productivity by reducing the overall data processing burden.
Data Source
AI summary
Methods of testing memory devices are disclosed. A method may include reading from a number of memory addresses of a memory array of the memory device and identifying each memory address of the number of addresses as either a pass or a fail. The method may further include storing, for each identified fail, data associated with the identified fail in a buffer of the memory device. Further, the method may include conveying, to a tester external to the memory device, at least some of the data associated with each identified fail without conveying address data associated with each identified pass to the tester. Devices and systems are also disclosed.