Memory Module Buffer Repair for Multi-Bit Hard Errors
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Solution Overview
Problem
Memory systems employing error codes face limitations in correcting multiple-bit errors, leading to premature failure of memory components when multiple hard errors occur, especially during assembly and testing of memory modules.
Innovation Solution
Incorporating a buffer circuit with error logic and repair logic within the memory module to identify and repair storage cell failures, allowing for in-module error correction and maintaining the error correction capability, thereby preventing recurring hard errors and extending the life of memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error codes with redundancy are used to detect and correct errors, then a limited number of data errors may be identified and corrected, but the overhead limits the effectiveness to single-bit error correction only
Solution Approach 1:
The patent segments the error correction function into two parts: (1) the original ECC code in the memory device handles single-bit errors, and (2) a separate error tracking and repair circuit in the buffer handles multi-bit errors by identifying and remapping defective cells. This segmentation allows each part to be optimized independently, maintaining low overhead while extending error correction capability to multiple bits.
Solution Approach 2:
The patent introduces a buffer as an intermediary component between the memory device and the memory controller. This buffer contains error tracking and repair circuits that act as a mediator to intercept and correct multi-bit errors before they reach the controller, thereby extending error correction capability without requiring changes to the memory device or controller designs.
2Productivity
If memory devices are assembled onto memory modules, then manufacturing efficiency is improved, but failures become more costly when modules are discarded for failing final testing
Solution Approach 1:
The patent implements error tracking and repair circuits during the module assembly process itself, allowing defective cells to be identified and repaired before final testing. This preliminary action prevents modules from failing during final testing, thereby reducing waste and improving manufacturing efficiency without compromising reliability.
Solution Approach 2:
The patent incorporates error repair capability as a cushioning mechanism during module assembly, where defective cells are proactively identified and remapped to spare cells before the module completes assembly. This beforehand cushioning ensures that modules pass final testing and reduces the costly discarding of failed modules.
3Reliability
If in-module error tracking and repair is implemented, then hard errors can be repaired and error correction capability maintained, but the buffer circuit complexity increases
Solution Approach 1:
The patent extracts the complex error tracking and repair logic from the main memory device or controller and places it solely in the buffer circuit. This extraction allows the memory device and controller to remain simple while the buffer handles all the complexity of multi-bit error correction, achieving a balance between reliability and overall system complexity.
Solution Approach 2:
The buffer circuit is designed to perform multiple functions: (1) standard data buffering, (2) error detection, (3) error tracking, and (4) repair remapping. By making the buffer multi-functional, the patent avoids adding separate dedicated circuits for each function, thereby limiting the increase in buffer complexity while achieving comprehensive error repair capability.
Data Source
AI summary
A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.