Memory Buffer ECC and Data Steering for Multi-Error Correction
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Solution Overview
Problem
Conventional memory systems struggle to effectively correct multi-errors in memory storage devices that are increasingly susceptible to interference due to shrinking storage cells, requiring significant changes to host controllers and system infrastructure, which negatively impact access latency and storage overhead.
Innovation Solution
A memory module with a memory buffer and an error detection and correction circuit that computes parity bits in parallel with data words, enabling detection and correction of single and multi-errors, and using data steering methods to direct data around faulty storage cells to redundant RAM chips or SRAM, ensuring data integrity without compromising system integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error detection and correction methods are used in memory systems, then single errors can be detected and corrected, but multi-errors cannot be corrected without significant changes to host controller and system infrastructure
Solution Approach 1:
The patent introduces a memory buffer as an intermediary component between the host controller and RAM chips. This buffer includes an integrated error detection and correction circuit that handles multi-error correction locally, eliminating the need to modify the host controller or system infrastructure. The buffer acts as a mediator that transparently corrects errors before data reaches the host controller, thereby improving reliability without increasing device complexity at the system level.
Solution Approach 2:
The memory buffer performs self-service by incorporating its own error detection and correction capabilities within its architecture. Rather than relying on external host controller functionality, the buffer autonomously detects and corrects multi-errors using integrated EDC circuits, parity bit computation, and data steering mechanisms. This self-contained approach allows the system to handle multi-errors without requiring changes to other system components.
2Reliability
If multi-error correction is implemented through host controller modifications, then multi-errors can be corrected, but access latency increases
Solution Approach 1:
The error detection and correction operations are performed preliminarily within the memory buffer before data is transferred to the host controller. Parity bits are computed and stored alongside data words during write operations, and error correction is performed during read operations before data leaves the memory module. This preliminary handling of error correction eliminates the need for additional host controller intervention that would otherwise increase access latency.
Solution Approach 2:
The memory buffer serves as an intermediary that handles error correction in parallel with normal memory operations. By processing error detection and correction within the buffer's internal circuitry rather than through host controller sequences, the system maintains normal access timing characteristics while still providing multi-error correction capability.
3Reliability
If multi-error correction is implemented through host controller modifications, then multi-errors can be corrected, but storage overhead increases
Solution Approach 1:
The patent employs parameter changes by using parity bits of varying lengths depending on the required error correction capability. The EDC circuit can operate with different parity bit configurations to correct different numbers of errors, allowing flexible adjustment of storage overhead based on specific application requirements. This parameter-based approach enables multi-error correction without fixed, excessive storage overhead.
Solution Approach 2:
The memory buffer intermediary manages storage overhead efficiently by implementing error correction codes that optimize the ratio of data to parity bits. The buffer's EDC circuit uses algorithms that provide multi-error correction capability with minimal additional storage requirements compared to host controller-based solutions, as the correction logic is integrated into the buffer's data path rather than requiring separate host controller storage structures.
Data Source
AI summary
The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another.