Memory Input Buffer Circuit With Current-Controlled Offset Cancellation
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Solution Overview
Problem
Conventional data input buffer circuits in semiconductor memory devices face challenges with slow operation due to high voltage differences between data input signals and reference voltages, leading to incomplete amplification and latch operations, and input offsets caused by transistor threshold voltage mismatches.
Innovation Solution
The proposed solution involves a data input buffer circuit design with P-channel and N-channel MOS transistors, flip-flop circuits, and current control circuits that adjust the amount of current based on code signals to minimize capacitance and offset errors, enabling faster operation and offset cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the voltage of the data input signal DQ and the reference voltage VREF are increased to meet LPDDR4 specification (VREF=42%*VDD), then the adaptability to wide input signal range is improved, but the input transistors M1 and M2 cannot be driven fast enough due to smaller VGS
Solution Approach 1:
The patent introduces a dynamic voltage adjustment mechanism where the power supply voltage to the first amplifier is varied based on the common-mode voltage level. When the common-mode voltage is high (42% of VDD), the amplifier receives a higher power supply voltage to maintain sufficient VGS and drive speed. When the common-mode voltage is low (10% of VDD), the amplifier receives a lower power supply voltage to maintain adequate voltage headroom for signal swing. This dynamic adjustment resolves the contradiction by adapting the power supply voltage to match the operating conditions.
Solution Approach 2:
The patent changes the power supply voltage parameter of the first amplifier dynamically based on the common-mode voltage level of the differential input signals. By adjusting this electrical parameter, the system maintains optimal transistor operation across different input voltage ranges, enabling both high common-mode voltage operation (42% VDD) and low common-mode voltage operation (10% VDD) to function correctly with appropriate drive speeds.
2Reliability
If the power supply voltage VDD is provided to nodes (node1 and node 2) to enable amplification, then the amplification capability is improved, but the time to increase voltages of the nodes and complete the sequence of amplification and latch operation is longer
Solution Approach 1:
The patent employs dynamic control of the power supply voltage to the first amplifier through a voltage selection circuit. Instead of using a fixed high power supply voltage that causes slow operation, the circuit dynamically selects between different power supply voltage levels based on the operating conditions. This dynamic adjustment enables the amplifier to operate faster by using higher power supply voltages when needed, while maintaining reliable amplification capability across different signal conditions.
3Device complexity
If conventional data input buffer circuits are used, then the circuit structure is simple, but the operation is slow due to high voltage differences and incomplete amplification and latch operations
Solution Approach 1:
The patent introduces dynamic voltage control into the conventional buffer structure by adding a voltage selection circuit that adjusts the power supply voltage to the first amplifier based on the common-mode voltage level. This dynamic element is integrated into the existing circuit architecture, maintaining relative simplicity while dramatically improving operation speed by ensuring the amplifier always operates with optimal voltage headroom regardless of the input signal level.
Data Source
AI summary
An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A potential of the first circuit node is changed based on an input signal. A flip-flop circuit includes first and second inverters cross-coupled to each other. The first inverter is coupled between the first voltage terminal and the second circuit node. A first transistor is coupled between the second and third circuit nodes, and the first transistor has a control electrode coupled to the first circuit node. A first current control circuit is coupled between the third circuit node and the second voltage terminal, and an amount of current flowing through the first current control circuit being controlled based on a first code signal.