Memory System Buffer Defect Detection via Parity Comparison
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Solution Overview
Problem
Memory systems face reliability issues due to defects in system buffers, where data errors can lead to incorrect address mapping and data loss, especially in volatile memory devices that lose data when power is lost.
Innovation Solution
A memory system with a system buffer and a buffer manager that generates and compares parity bits to detect defective addresses, blocking access to these addresses and replacing them with functional ones to maintain data integrity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory devices are used for system buffer, then speed is improved, but reliability deteriorates due to data loss when power is lost
Solution Approach 1:
The patent applies preliminary action by generating and storing parity bits for each buffer area before actual data storage. The buffer manager pre-calculates parity bits based on data to be stored in the system buffer, and stores these parity bits in association with buffer area addresses. This preliminary preparation enables subsequent error detection without sacrificing the high-speed characteristics of volatile memory.
2Reliability
If defect detection and blocking mechanisms are added, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary mechanism - the buffer manager - that mediates between the host and the system buffer. The buffer manager handles parity bit generation, storage, and comparison operations, as well as defect detection and address remapping. This intermediary layer provides systematic error handling without requiring changes to the underlying volatile memory structure, thus improving reliability while maintaining relatively simple device architecture.
Data Source
AI summary
Memory systems and operating methods of the memory systems are disclosed. In an implementation, a memory system includes a system buffer including buffer areas to which addresses are allocated, and configured to store data in the buffer areas, and a buffer manager configured to designate an address of a buffer area in which a defect occurs as a defect address by comparing a first parity bit for data stored in the system buffer with a second parity bit that is obtained by a computation based on the data stored in the system buffer, and block access to the buffer area designated as the defect address.