Semiconductor Memory Device Buffer Segmentation
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Solution Overview
Problem
Conventional semiconductor memory devices experience increased data processing time due to high capacitance in data transmission lines, which is exacerbated by the length of buffers, leading to slower data processing speeds and longer precharging times.
Innovation Solution
The semiconductor memory device incorporates data transmission lines shorter than the length of buffers, along with a path multiplexing unit that selects data transmission paths based on addresses, reducing capacitance and optimizing data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission lines are extended to cover the full length of buffers, then all buffers can be connected to bit lines, but capacitance increases leading to slower data processing speed
Solution Approach 1:
The patent divides the buffer array into multiple segments, each segment connected to bit lines through separate data transmission lines. This segmentation allows shorter transmission lines within each segment, reducing capacitance and precharging time while still providing access to all buffers through the segmented structure.
Solution Approach 2:
The patent introduces a new dimensional organization by arranging buffers in a two-dimensional array structure with row buffers and column buffers, rather than a single linear sequence. This spatial reorganization enables multiple shorter transmission paths to serve the same functional purpose, reducing the length of individual data transmission lines and their associated capacitance.
2Productivity
If data transmission lines are shortened, then capacitance is reduced and data processing speed is improved, but the number of transmission lines must be increased requiring path multiplexing
Solution Approach 1:
The path multiplexing unit is designed to serve multiple functions: it selects active data transmission lines based on buffer addresses, manages the routing between segmented buffers and bit lines, and coordinates the operation of multiple transmission lines. This multi-functional design consolidates control logic that would otherwise be distributed, managing complexity while enabling the benefits of shorter transmission lines.
3Ease of manufacture
If buffers are arranged in a linear sequence, then layout is simple, but data transmission lines become excessively long increasing capacitance
Solution Approach 1:
The patent transforms the linear one-dimensional buffer arrangement into a two-dimensional array structure with row and column dimensions. This dimensional change allows data transmission lines to access buffers in a more compact spatial configuration, significantly reducing the length and capacitance of transmission lines while maintaining systematic layout organization through the dimensional grid structure.
Data Source
AI summary
A semiconductor memory device includes a memory bank configured to store data, a buffering unit including a plurality of buffers, which are disposed to extend to a X-axis of the memory bank to store data transferred from the memory bank, a plurality of data transmission lines configured to transfer the data stored in the plurality of buffers, and a path multiplexing unit configured to select one of a plurality of data transmission paths in response to addresses and transfer the data through the selected data transmission path.