Memory Controller Buffer Pattern Correction for Cell Coupling Errors
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Solution Overview
Problem
High-density recording in nonvolatile memory devices leads to increased capacitive coupling between memory cells, causing data garbling and irrecoverable errors, even with high error correcting codes, due to the proximity of neighboring cells.
Innovation Solution
A memory device with a data pattern check circuit and a data correction circuit that temporarily stores data in a buffer, checks for predetermined data patterns, and corrects or inverts data values before writing to prevent garbling by adjusting the data pattern, thereby enhancing reliability and reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-density recording is performed to increase memory capacity, then memory capacity increases, but capacitive coupling between neighboring memory cells increases causing data garbling
Solution Approach 1:
The patent applies preliminary action by checking data patterns before writing to memory. The data pattern check circuit detects problematic patterns (such as alternating 0s and 1s) that would cause capacitive coupling issues, and corrects them in advance by inverting affected bits. This prevents data garbling before it occurs, allowing high-density recording while maintaining data accuracy.
2Manufacturing precision
If microfabrication is advanced to decrease distance between memory cells, then integration density increases, but capacitive coupling increases causing data garbling
Solution Approach 1:
The patent applies preliminary anti-action by introducing a data pattern check circuit that identifies and corrects problematic data patterns before they are written to memory. The circuit detects patterns that would exacerbate capacitive coupling effects (such as alternating 0s and 1s in adjacent cells) and inverts the affected bits in advance. This counteracts the harmful capacitive coupling effect before it can cause data garbling, enabling advanced microfabrication while maintaining data integrity.
3Reliability
If error correcting code with high error correcting capability is used, then error correction capability increases, but data garbling becomes irrecoverable when capacitive coupling occurs
Solution Approach 1:
The patent applies preliminary action by performing data pattern checking and correction before data is written to memory. The data pattern check circuit identifies patterns that would cause capacitive coupling-induced errors, and the data correction circuit inverts affected bits in advance. This prevents data garbling before storage, making error recovery unnecessary even though ECC is available, thereby eliminating data irrecoverability issues.
4Productivity
If data is written directly to memory without checking, then writing speed increases, but data garbling occurs due to capacitive coupling
Solution Approach 1:
The patent applies preliminary action by implementing a data pattern check circuit that operates in parallel with the data writing process. The circuit checks for problematic patterns (such as alternating 0s and 1s) and corrects them by inverting affected bits before the data is latched and written to memory. This preliminary correction maintains high writing speed while preventing data garbling, as the correction occurs in the data path without requiring separate correction cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents data garbling, improves reliability, and allows for higher integration density without the need for extensive error correction, reducing the number of correction positions and enhancing decoding performance.
Implementation Method 1
the value of capacitive coupling occurring between the floating gates (FG) of neighboring memory cells increases
Data Source
AI summary
A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory.