Memory Controller Buffer Deallocation for Power-Loss Data Transfer

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Solution Overview

Problem

Existing memory systems face challenges in efficiently managing power loss scenarios by effectively transferring data from volatile to non-volatile memory while optimizing buffer usage and reducing latency during power loss events.

Innovation Solution

A memory system with a memory controller that allocates and deallocates buffer areas based on usage thresholds, switches write operations to a more efficient mode during power loss, and prioritizes data transfer to non-volatile memory using a capacitor for power backup.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the memory system writes data from volatile memory to non-volatile memory during power loss using capacitor energy, then data integrity is maintained, but the time available for data transfer is limited

Engineering Contradiction:
Improvedata integrityVSAvoidtime available for data transfer
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary actions by detecting power loss conditions and initiating data transfer from volatile to non-volatile memory before the capacitor energy is fully depleted. The controller prioritizes data transfer operations and manages buffer allocation to ensure critical data is saved during the limited time window provided by capacitor discharge.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the memory controller deallocates buffer areas frequently to optimize usage, then buffer efficiency improves, but system complexity increases

Engineering Contradiction:
Improvebuffer efficiencyVSAvoidcontroller complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory controller implements feedback mechanisms by continuously monitoring buffer usage levels and dynamically adjusting deallocation decisions. The controller tracks which buffer areas have completed data-in operations and uses this information to determine optimal deallocation timing, balancing buffer efficiency with operational simplicity.

Inventive Principle:
Principle #23Feedback

3Reliability

If the memory system uses a capacitor for power backup during power loss, then data transfer capability is maintained, but the energy available is limited

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidenergy available for data transfer
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system maintains continuous useful action by keeping the capacitor charged during normal operation and immediately utilizing its stored energy upon power loss detection. The controller manages the capacitor's energy discharge continuously to sustain data transfer operations throughout the available time window, ensuring uninterrupted data protection functionality.

Inventive Principle:
Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances data integrity by ensuring seamless data transfer to non-volatile memory during power loss, optimizing buffer usage, and minimizing latency by adapting write operations to reduce power consumption and maintain system performance.

Implementation Method 1

The memory system may have a capacitor. In a case where power loss is detected, the memory system writes data stored in the volatile memory to the nonvolatile memory by using electric energy stored in the capacitor.

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12578873B2Memory system and method
Publication Date: 2026.03.17 KIOXIA CORP
  • US12578873B2 patent drawing
  • US12578873B2 patent drawing
  • US12578873B2 patent drawing

AI summary

According to an embodiment, a memory system includes a memory controller. At a first timing within a period from allocation of an area unit to completion of a data-in operation on the data unit stored in an area unit, the memory controller deallocates the area unit upon the completion of the data-in operation on the data unit when a usage of a buffer area is smaller than a first threshold value. At the first timing, the memory controller deallocates the area unit upon completion of the program operation on the data unit when the usage of the buffer area is larger than a second threshold value. The second threshold value is larger than the first threshold value.