Memory Rank CA Buffer Powerdown Modes for Faster Exit

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Solution Overview

Problem

Semiconductor memory devices face performance issues due to the long time required for input buffers to exit power down, which affects power consumption and operational efficiency.

Innovation Solution

Implementing multiple powerdown modes, including a first mode where input buffers are powered down completely for a slow exit and a second mode where they are powered down incompletely for a fast exit, reducing power consumption and exit time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If input buffers are powered down completely to reduce power consumption, then power consumption is reduced, but the time required to exit power down increases

Engineering Contradiction:

Improvepower consumptionVSAvoidexit power down time

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent implements dynamic power management by providing multiple power down modes (first power down mode with complete power down and slow exit, second power down mode with incomplete power down and fast exit) that allow the system to adapt between power consumption and exit time based on operational requirements

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the power down parameters by introducing different power down modes with varying degrees of power down (complete vs. incomplete) and corresponding exit times (slow vs. fast), allowing optimization based on specific operational contexts

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If input buffers are powered down to reduce power consumption, then power consumption is reduced, but device performance is adversely impacted

Engineering Contradiction:

Improvepower consumptionVSAvoiddevice performance

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The system dynamically selects between different power down modes based on performance requirements, using the second power down mode (incomplete power down) when fast response is needed to maintain performance while still achieving power savings

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

By changing the power down state parameters (complete vs. incomplete power down), the system can adjust the balance between power consumption and performance, allowing the buffers to exit faster when performance is critical

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20260037053A1Apparatuses and methods for multiple power down and exit modes in memory devices

Publication Date: 2026.02.05 MICRON TECHNOLOGY INC

AI summary

A memory device can operate in multiple powerdown modes. A first powerdown mode powers down a memory rank by powering down one or more command address (CA) input buffers completely (e.g., turn off). A second powerdown mode powers down a memory rank by powering down one or more command address (CA) input buffers incompletely (e.g., a reduced operational state). In a non-limiting nonexclusive embodiment, the second powerdown mode powers down the one or more CA input buffers by placing the one or more CA input buffers in a low bias current state.