Multi-bit Memory Buffer Program Scheduling for Reliability
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Solution Overview
Problem
The reliability of multi-bit memory devices is compromised due to variations in threshold voltages caused by coupling between adjacent memory cells, making it difficult to securely store and read multi-bit data.
Innovation Solution
Implementing a multi-bit memory device with a memory cell array divided into two regions, where one region stores 1-bit data and the other stores M-bit data, using a memory controller to manage a buffer program operation and a main program operation through static or dynamic scheduling based on performance thresholds, and employing a 1-step, coarse, and fine program operation sequence to manage threshold voltage distributions and reduce coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data is stored in adjacent memory cells to increase storage density, then storage capacity is improved, but threshold voltage variations due to coupling between cells increase, worsening data reliability
Solution Approach 1:
The memory cell array is divided into a first region for 1-bit data and a second region for M-bit data. This segmentation isolates multi-bit storage into a dedicated region, reducing coupling interference from adjacent cells while maintaining high storage capacity in the second region.
Solution Approach 2:
A buffer memory is introduced as an intermediary between the host and memory cell array. The buffer temporarily stores data during programming operations, allowing controlled transfer of data to either the first or second region based on scheduling decisions, thereby managing the trade-off between storage capacity and reliability.
2Productivity
If buffer program operation is continuously executed to improve processing efficiency, then productivity is improved, but main program operations are delayed, worsening data storage timeliness
Solution Approach 1:
The scheduling manner is made dynamic rather than fixed. The memory controller selectively switches between static scheduling (sequential execution) and dynamic scheduling (concurrent execution with delays) based on real-time performance measurements, allowing the system to adapt to varying workload conditions and optimize both productivity and timeliness.
Solution Approach 2:
The system changes operational parameters by adjusting the scheduling strategy based on measured performance metrics. When performance falls below targets, the system transitions to dynamic scheduling with adjusted timing parameters for main program operations, thereby optimizing the balance between processing efficiency and storage timeliness.
3Device complexity
If static scheduling manner is used to simplify control logic, then device complexity is reduced, but processing flexibility is limited, worsening adaptability to performance variations
Solution Approach 1:
The scheduling system transitions from a purely static approach to a dynamic adaptive approach. The memory controller includes performance measurement and judgment circuits that automatically select between static and dynamic scheduling manners based on measured performance, providing adaptability without significantly increasing control logic complexity through modular design.
Solution Approach 2:
The memory controller performs self-adjustment by automatically measuring its own performance and selecting appropriate scheduling manners without external intervention. This self-service capability enables the system to adapt to performance variations autonomously, maintaining flexibility while keeping the control mechanism relatively simple.
Data Source
AI summary
Disclosed is an on-chip buffer program method for a data storage device which comprises a multi-bit memory device and a memory controller. The on-chip buffer program method includes measuring a performance of the data storage device, judging whether the measured performance satisfies a target performance of the data storage device, and selecting one of a plurality of scheduling manners as an on-chip buffer program scheduling manner of the data storage device according to the judgment result.