Multi-chip Memory Buffer for Program Time Reduction
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Solution Overview
Problem
The speed of multi-chip flash memory devices with Multi-Level Cell (MLC) technology is hindered by increased read and program times as the number of bits stored increases, limiting the data throughput and operational efficiency of these devices.
Innovation Solution
Implementing a buffer section within the MLC memory device that operates as a Single Level Cell (SLC) or a 2-bit MLC, allowing for temporary storage of data and subsequent transfer to a primary MLC array section during idle times, thereby optimizing data handling and reducing program times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC stores more bits per cell, then storage capacity increases, but program time and read time increase
Solution Approach 1:
The patent divides the MLC memory system into multiple independent memory chips, each handling specific data operations. By segmenting the storage across multiple chips, the system can perform parallel read and program operations, thereby reducing the overall program time while maintaining high storage capacity through the multi-bit MLC cells.
Solution Approach 2:
The patent implements a buffer section that temporarily stores data before it is programmed into the MLC array. This preliminary buffering allows data to be prepared and staged for programming, enabling more efficient use of the programming process and reducing the effective program time by avoiding repeated access and re-programming operations.
2Quantity of substance
If MLC stores more bits per cell, then storage capacity increases, but read time increases
Solution Approach 1:
By dividing the memory into multiple chips with dedicated read functions, the system can perform parallel read operations. Each chip can be read simultaneously, reducing the total read time while maintaining the high storage capacity provided by MLC's multi-bit cells.
Solution Approach 2:
The buffer section acts as an intermediary between the MLC array and the external interface. It can hold recently accessed data, allowing rapid retrieval without requiring full MLC read cycles, thereby reducing effective read time while preserving the high-density storage capability.
3Area of stationary object
If multi-chip package is used, then miniaturization and packaging area are improved, but data throughput is limited by operation speed
Solution Approach 1:
The multi-chip package uses multiple independent memory chips that can operate in parallel. Each chip handles specific data operations simultaneously, which maintains the space efficiency of multi-chip packaging while dramatically increasing data throughput through parallel processing of read and program operations.
Solution Approach 2:
The buffer section pre-processes and stages data before it enters the MLC array, and can also hold data for rapid output. This preliminary action ensures that data is ready for transfer when needed, maximizing data throughput from the compact multi-chip package without requiring larger physical dimensions.
Data Source
AI summary
Multi-chip package devices and related data programming methods are disclosed. A multi-chip package device includes one or more memory chips and a controller. The one or more memory chips include a single level cell section and a multi level cell section. The controller is configured to control a first data storing operation for storing an input data to the single level cell section and control a second data storing operation for storing the input data stored in the single level section to the multi level cell section during an idle time.