Memory Control Output Buffer With Idle-State Pull-Up Control
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Solution Overview
Problem
Semiconductor integrated circuits face deterioration of transistor characteristics over time, leading to decreased signal reception margins, especially at high operating frequencies, due to the transistor's conductive state and high impedance states, which can result in erroneous output signals.
Innovation Solution
A semiconductor integrated circuit design that includes an output buffer, power supply control circuit, pull-up control circuit, and control signal generating circuit to manage the supply of power and pull-up control signals, preventing the output terminal from entering a high impedance state by controlling the enable signals and ensuring proper voltage levels during idle and output periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the output terminal is set to a high impedance state during idle periods, then power consumption is reduced, but erroneous output signals may be generated due to noise effects
Solution Approach 1:
The patent applies preliminary action by setting the output terminal to a predetermined voltage level (VDD or GND) before the idle period begins. The control signal generating circuit generates control signals that switch the output terminal to a defined voltage state in advance, preventing the high impedance state that would otherwise occur during idle periods. This preliminary positioning of the output terminal to a known voltage state eliminates noise susceptibility while maintaining power efficiency.
2Reliability
If the pull-up transistors are constantly in the conductive state, then the output terminal maintains a defined voltage level, but transistor characteristics deteriorate over time due to continuous conduction
Solution Approach 1:
The patent implements periodic action by switching the pull-up transistors between conductive and non-conductive states based on periodic control signals. During output periods, the pull-up transistors are activated to maintain the output terminal at a defined voltage level. During idle periods, the pull-up transistors are deactivated to prevent continuous conduction and reduce deterioration. This periodic switching pattern, controlled by the control signal generating circuit, allows the output terminal to maintain stability when needed while reducing stress on the transistors during idle times.
3Duration of action of stationary object
If the pull-up transistors are switched between conductive and non-conductive states according to output signals, then transistor deterioration is reduced, but erroneous output signals may be generated due to noise effects when the output terminal is in high impedance state
Solution Approach 1:
The patent uses an intermediary approach by introducing a control signal generating circuit that produces dedicated control signals (first control signal and second control signal) to manage the pull-up transistor states. These control signals act as intermediaries between the output signals and the pull-up transistor switching, ensuring that the transistors are switched to defined voltage states during idle periods rather than entering high impedance states. This intermediary control mechanism prevents noise-induced erroneous outputs while still allowing periodic switching to reduce transistor deterioration.
4Reliability
If the transistor characteristics deteriorate due to continuous conductive state, then the signal reception margin decreases, but constantly maintaining the output terminal at a defined voltage requires continuous power supply
Solution Approach 1:
The patent applies periodic action by controlling the power supply to the output buffer and pull-up transistors through periodic enable signals. During output periods, power is supplied to maintain the output terminal at a defined voltage level and ensure proper signal transmission. During idle periods, power supply is reduced or stopped, allowing the system to enter a low-power state. The control signal generating circuit coordinates these periodic power supply adjustments with the transistor switching patterns, ensuring that signal reception margin is maintained during active periods while achieving power savings during idle periods.
Data Source
AI summary
A semiconductor integrated circuit includes a buffer which outputs a memory control signal to a terminal coupled to a memory device, a power supply control circuit which controls a supply of a power supply voltage from a power supply line to the buffer based on a power control signal, a pull-up control circuit configured to control a pull-up of the terminal based on a pull-up control signal, and a control signal generating circuit. The control signal generating circuit generates, during an output period, the power control signal to supply the power supply voltage to the buffer, and the pull-up control signal to stop the pull-up of the terminal, and generates, during an idle period, the power control signal to stop the supply of the power supply voltage to the buffer, and the pull-up control signal to perform the pull-up of the terminal.