Memory Buffer Register File for Simultaneous Row Access
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Solution Overview
Problem
Conventional memory systems experience performance degradation during data read/write operations due to limitations in accessing multiple row addresses within the same bank of DRAM chips, leading to increased read times and inability to improve performance even with a memory buffer.
Innovation Solution
A memory system with a memory buffer that includes a register file with multiple entry spaces, allowing simultaneous access to different address areas, and an address converter that converts non-simultaneously accessible first addresses into simultaneously accessible second addresses, enabling efficient read/write operations across multiple memory modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple row addresses in the same bank are accessed sequentially, then the memory system can handle complex access patterns, but the read time increases and performance degrades
Solution Approach 1:
The memory buffer is segmented into multiple entry spaces (first entry space, second entry space, etc.) corresponding to different interleaving units of the memory module. Each entry space can independently store data from different row addresses, allowing parallel access to multiple banks simultaneously. This segmentation enables the system to maintain adaptability for complex access patterns while reducing read time through parallel operations.
2Ease of operation
If a conventional memory buffer with FIFOs is used, then data can be temporarily stored during read/write operations, but performance degradation cannot be prevented when accessing multiple row addresses in the same bank
Solution Approach 1:
The patent transitions from a single-dimension FIFO buffering approach to a multi-dimensional address mapping approach. The address converter maps first addresses (which may refer to the same bank) to second addresses that distribute data across multiple entry spaces in different address areas. This dimensional transformation allows the memory buffer to handle multiple row addresses in parallel, improving productivity while maintaining ease of operation.
3Device complexity
If row addresses in the same bank are successively accessed, then the memory system can maintain simple address mapping, but performance improvement cannot be expected due to sequential access requirements
Solution Approach 1:
The address converter acts as an intermediary between the host's address requests and the memory buffer's physical storage locations. It translates first addresses into second addresses that distribute access across multiple entry spaces, enabling parallel access without increasing host-side complexity. This intermediary layer maintains simple address mapping from the host perspective while achieving high productivity through internal parallelization.
Data Source
AI summary
A memory system may include a memory module accessed by a first address, a memory controller configured to provide a read or write command for the memory module according to a host request, and a memory buffer accessed by a second address. The memory buffer may include a register file having two or more entry spaces corresponding to interleaving units of the memory module, and the two or more entry spaces may be positioned in different address areas which are accessible at the same time.