Memory Buffer Segmentation for Write Latency Control
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Solution Overview
Problem
The existing NAND flash memory systems face inefficiencies in data relocation during garbage collection, leading to increased latency for write accesses due to the need for resource management and the inability to overwrite or erase data in smaller units than a block, which affects the memory system's performance.
Innovation Solution
A memory system configuration that includes a resource management circuit with a timer and separate buffers for host writes and garbage collection writes, allowing for the allocation of specific buffer areas at predetermined intervals to mitigate latency fluctuations by ensuring continuous data transfer from the host to the NAND memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If garbage collection is initiated to relocate data in NAND memory, then data relocation is achieved, but resources are spent and write access latency deteriorates
Solution Approach 1:
The buffer memory is segmented into a first buffer area for host write operations and a second buffer area for garbage collection operations. This segmentation allows independent management of resources for host writes and data relocation, enabling the system to perform garbage collection without completely blocking host write access to the buffer, thereby reducing write access latency while maintaining data relocation capability.
Solution Approach 2:
The buffer area allocation is made dynamic rather than fixed. The memory controller can dynamically allocate and reallocate buffer areas between host writes and garbage collection based on current system state and workload demands. This dynamic adjustment allows the system to optimize performance by giving priority to host writes when needed while still performing garbage collection, thus resolving the latency issue.
2Productivity
If data relocation is performed during garbage collection, then empty blocks are generated, but resources are consumed and write performance deteriorates
Solution Approach 1:
By dividing the buffer into separate first and second buffer areas, the system can perform data relocation in the second buffer area without preventing the first buffer area from accepting new host writes. This segmentation enables concurrent operations, improving data relocation efficiency while maintaining write access performance.
Solution Approach 2:
The buffer memory acts as an intermediary between the host and NAND memory. During garbage collection, the buffer mediates by temporarily storing relocated data in the second buffer area while allowing the first buffer area to continue receiving host writes. This intermediary role smooths out the performance impact of data relocation.
Data Source
AI summary
According to one embodiment, a memory includes a non-volatile memory, a first buffer, a first circuit, a second circuit, and a third circuit. The first circuit transfers data from a host to the non-volatile memory through the first buffer. The second circuit executes garbage collection through the first buffer. The first buffer includes a second buffer and a third buffer. The second buffer can be allocated to the first and second circuit. The third buffer can be allocated only to the first circuit. The third circuit includes a timer. The third circuit allocates the first buffer to the first circuit or the second circuit upon writing of data in the non-volatile memory from the second buffer. The third circuit, after data is written into the non-volatile memory from the third buffer, allocates the third buffer to the first circuit at timing based on the timer.