Semiconductor Memory Buffer Control for Self-Refresh Power
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Solution Overview
Problem
Semiconductor memory devices face high current consumption during refresh operations, particularly in self-refresh mode, due to the continuous activation of command and address buffers, which is unnecessary and inefficient.
Innovation Solution
A semiconductor memory device design that includes a buffer control unit to disable command and address buffers during self-refresh mode and enable them only when necessary, such as when exiting the self-refresh mode or performing specific operations, thereby reducing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If command buffers and address buffers are continuously enabled to receive commands and addresses, then the memory device can respond to external commands quickly, but current consumption increases during refresh operations
Solution Approach 1:
The patent applies dynamics by making the buffer enable state changeable based on operational mode. The buffer control unit dynamically adjusts the enable state of command buffers and address buffers according to whether the device is in refresh mode or normal operation mode, allowing the system to adapt its resource usage to current needs and reduce unnecessary power consumption during refresh operations
Solution Approach 2:
The buffer control unit automatically manages the enable state of buffers based on mode signals without requiring external intervention. When entering refresh mode, the control unit self-manages disabling the buffers, and when exiting refresh mode, it automatically re-enables them, making the power management autonomous and integrated into the existing control logic
2Productivity
If multiple command buffers and address buffers are used to handle multiple commands and addresses, then the memory device can process multiple operations efficiently, but the device complexity and current consumption increase
Solution Approach 1:
The patent extracts the power management function from the buffer control logic by introducing a dedicated buffer control unit. This separate unit specifically manages the enable states of command buffers and address buffers based on operational mode, isolating the power control functionality from the main buffer operation logic and simplifying the overall system architecture
Solution Approach 2:
The buffer control unit serves multiple functions: it monitors mode signals, determines buffer enable states, and controls the activation of multiple buffers simultaneously. This single control unit handles power management for both command buffers and address buffers, reducing the need for separate control circuits for each buffer and thereby reducing device complexity
Data Source
AI summary
A semiconductor memory device includes a memory cell array configured to include a plurality of word lines, a dock enable buffer configured to receive a clock enable signal, a plurality of command buffers configured to receive a plurality of commands, a refresh control unit configured to sequentially activate the plurality of word lines in a self-refresh mode, a command decoder configured to decode the clock enable signal and the plurality of commands, and to allow the refresh control unit to enter the self-refresh mode or exit from the self-refresh mode, and a buffer control unit configured to disable the plurality of command buffers when the clock enable signal is deactivated, and to enable the plurality of command buffers when the refresh control unit exits from the self-refresh mode.