Memory Buffer Autonomous Sparing for Hidden Regions

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Solution Overview

Problem

Conventional memory sparing systems in information handling systems (IHS) are limited as they require a memory controller, are not available on all processor types, and cannot effectively manage memory regions hidden from the controller, leading to incomplete protection and system operation interruptions during failures.

Innovation Solution

A memory controller-independent memory sparing system that uses a memory buffer and firmware to perform copy operations between memory regions without instruction from the memory controller, utilizing calibration and refresh periods to execute copy operations and manage sparing status, allowing for flexible and autonomous memory protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory sparing is controlled by a memory controller, then memory sparing associations can be managed centrally, but memory regions hidden from the controller are excluded from protection and system operations are interrupted during failures

Engineering Contradiction:
Improvememory protection coverageVSAvoidmemory controller dependency
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the memory sparing control function from the memory controller and relocates it to the memory buffer. This allows memory regions previously hidden from the controller to be included in sparing associations, achieving complete coverage without controller intervention during copy operations.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The memory buffer performs copy operations autonomously without requiring memory controller intervention. When a failure is detected, the buffer independently initiates and executes data copying to spare regions, eliminating system interruptions and maintaining operation continuity.

Inventive Principle:
Principle #25Self-service

2Adaptability or versatility

If memory sparing requires uniform population of DIMMs across the IHS, then memory sparing associations can be simplified, but the ability to create different levels of protection based on memory regions is limited

Engineering Contradiction:
Improvememory protection flexibilityVSAvoidDIMM configuration constraints
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic sparing associations where the memory buffer can flexibly configure which memory regions are protected and by which spare regions. This allows different levels of protection for different memory regions based on their importance, without requiring uniform DIMM populations across the system.

Inventive Principle:
Principle #15Dynamics

3Productivity

If the memory buffer performs copy operations autonomously, then system operations are not interrupted during failures, but the memory buffer must manage copy operations without controller instruction

Engineering Contradiction:
Improvesystem operation continuityVSAvoidbuffer autonomy level
Core Design Contradiction:
ProductivityVSExtent of automation

Solution Approach 1:

The memory buffer maintains sparing associations and identifies spare regions in advance, so when a failure occurs, copy operations can immediately begin without waiting for controller instructions. This preliminary preparation ensures system operations continue uninterrupted during the actual copy process.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP2828756B1Memory controller-independent memory sparing
Publication Date: 2017.01.18 DELL PROD LP
  • EP2828756B1 patent drawingFigure 1
  • EP2828756B1 patent drawingFigure 2
  • EP2828756B1 patent drawingFigure 3

AI summary

An information handling system (IHS) includes a memory controller, a memory device, and firmware. A failing memory region and a spare memory region are included on the memory device. A memory buffer in the memory device is coupled to the failing memory region and the spare memory region. The memory buffer is operable to perform copy operations without instruction from the memory controller in order to copy data from the failing memory region to the spare memory region in response to firmware operations performed by the firmware. Firmware operations may include instructing the memory controller to produce additional refresh or calibration operation time periods, or providing an instruction to perform a data transfer operation to the spare memory region. The memory buffer is also operable to route requests from the memory controller to one of the failing memory region and the spare memory region during the copy operations.