Memory Buffer Timing Adjustment for Signal Integrity
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Solution Overview
Problem
High-speed data transfer in memory modules is hindered by increased load capacitance, leading to signal quality deterioration, and existing solutions like Fully-Buffered type memory modules are costly due to high-performance Advanced Memory Buffers, while Load Reduced type modules lack optimal timing adjustments.
Innovation Solution
Implementing a controller with pre-launch and post-launch circuits to adjust the output timing of command/address and control signals, respectively, with a fine time adjustment resolution to ensure setup and hold margins, and incorporating a training function for optimal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory modules are installed to increase memory capacity, then memory capacity is improved, but load capacitance of data line increases and signal quality deteriorates
Solution Approach 1:
A buffer chip is introduced as an intermediary component between the memory controller and memory chips. The buffer chip receives data from the memory controller, temporarily stores it, and then supplies it to the memory chips. This intermediary structure isolates the memory controller from the capacitive load of multiple memory modules, reducing the load capacitance seen by the data line and improving signal quality while maintaining high memory capacity.
2Reliability
If Fully-Buffered type memory module with Advanced Memory Buffer is used to reduce load capacitance, then load capacitance of data line is reduced, but cost and power consumption increase
Solution Approach 1:
The patent changes the operational parameters of the buffer chip, specifically operating it at lower voltage levels (e.g., 1.5V or 1.35V) compared to high-performance Advanced Memory Buffers. This parameter change reduces power consumption and allows the use of less expensive buffer chips while still achieving the required load capacitance reduction for high-speed operation.
Solution Approach 2:
The patent employs standard, commercially available buffer chips rather than expensive high-performance Advanced Memory Buffers. These conventional buffer chips are more cost-effective and widely available, reducing the overall cost of the memory module while still providing sufficient buffering capability to reduce load capacitance on the data line.
3Reliability
If Fully-Buffered type memory module with Advanced Memory Buffer is used, then load capacitance is reduced, but interface compatibility with memory controller is lost
Solution Approach 1:
The buffer chip is designed with universal interfaces that are compatible with standard memory controller protocols. The buffer chip can interface with conventional memory controllers using standard signaling, maintaining compatibility and allowing off-the-shelf memory controllers to be used. This universal design enables the buffer to work with various memory controller implementations without requiring specialized interfaces.
4Productivity
If high data transfer rate is implemented, then productivity is improved, but signal quality deteriorates due to load capacitance
Solution Approach 1:
The buffer chip performs preliminary actions by pre-charging and pre-conditioning data signals before they are transmitted to the memory chips. It also pre-manages the timing and sequencing of data transfers, preparing signals in advance to compensate for the effects of load capacitance. This preliminary action ensures that signals arrive at the memory chips with adequate timing margins and voltage levels, enabling high-speed operation without signal integrity issues.
Data Source
AI summary
A memory buffer mounted on a memory module includes a pre-launch function of advancing outputs of address/command signal and a post-launch function of delaying outputs of control signal. A time step increment for pre/post-launch time adjustment is set to be equal to or finer than tCK/32 where tCK is one clock cycle.