Duty-Corrected Memory Buffer for Wider Toggle Signal Windows
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Solution Overview
Problem
In high-speed data transmission, securing a valid data window for toggle signals is challenging due to increased toggling frequency, leading to duty distortion and reduced system speed and reliability.
Innovation Solution
A storage system with a memory controller, buffer, and nonvolatile memory that performs duty cycle correction on clock and data strobe signals using samplers, comparators, and logic circuits to maintain a stable duty ratio, ensuring accurate data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the toggling frequency of the toggle signal is increased to transmit large amounts of data at high speed, then the data transmission speed is improved, but the duty distortion increases and the valid data window becomes insufficient
Solution Approach 1:
The patent applies preliminary action by performing duty cycle correction in advance before data transmission. The duty cycle corrector pre-adjusts the clock signal to compensate for expected duty distortion, ensuring that even at high toggling frequencies, the valid data window remains sufficient for reliable data sampling.
Solution Approach 2:
The patent implements feedback through the duty cycle correction mechanism that monitors and adjusts the clock signal duty cycle. The system continuously detects duty distortion and applies corrective adjustments, creating a closed-loop control system that maintains reliable data transmission despite high-speed operation.
2Productivity
If the toggling frequency of the toggle signal is increased to transmit large amounts of data at high speed, then the data transmission speed is improved, but the valid data window becomes insufficient
Solution Approach 1:
The duty cycle corrector performs preliminary adjustment of the clock signal duty cycle before data transmission occurs. By pre-correcting the duty cycle at higher toggling frequencies, the system ensures that each data pulse maintains an adequate valid window duration despite the reduced time available at higher speeds.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the duty cycle of the clock signal based on the toggling frequency. When the toggling frequency increases, the system modifies the duty cycle parameter to maintain an appropriate valid data window duration, balancing throughput and reliability.
3Reliability
If duty cycle correction operations are performed on clock and data strobe signals, then the data transmission reliability is improved, but the device complexity increases
Solution Approach 1:
The patent merges the duty cycle correction functionality into the existing buffer structure. By integrating the duty cycle corrector with the buffer that already handles data strobe signals, the system achieves reliable data transmission without adding completely separate correction circuits, thereby reducing overall device complexity.
Solution Approach 2:
The buffer structure is designed to perform multiple functions simultaneously: it buffers data signals, generates data strobe signals, and performs duty cycle correction on both clock and data strobe signals. This multi-functionality reduces the need for separate dedicated circuits for each function, simplifying the overall device architecture.
Data Source
AI summary
A storage system includes a memory controller providing a clock signal; a buffer having a first duty cycle corrector to receive the clock signal and a chip selection signal from the memory controller, perform a first duty correction operation on the clock signal using a first data code and output a first corrected clock signal, a register to store the first data code regarding the chip selection signal, and a sampler to receive a data signal and a data strobe signal regarding the data signal and output a data stream; and a nonvolatile memory having a second duty cycle corrector to receive the first corrected clock signal from the buffer and perform a second duty correction operation on the first corrected clock signal using a second data code and out a second corrected clock signal, a second data code generation circuit to generate the second data code based on the second corrected clock signal, and a data strobe signal generator to generate the data strobe signal based on the second corrected clock signal and provide the data strobe signal to the buffer.