Memory Device Buffer Reset for Data Under-Run Detection

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Solution Overview

Problem

Existing memory devices face issues with data under-run during transmission, leading to incomplete data storage that cannot be recovered, which affects data reliability.

Innovation Solution

A memory device with a cell region and peripheral region, including a buffer region, that synchronizes data with a clock signal and resets the buffer region upon detecting an under-run based on clock signal count values, ensuring complete data storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data transmission rate is increased to improve communication efficiency, then productivity is improved, but under-run occurs during data transmission leading to data loss

Engineering Contradiction:
Improvedata transmission rateVSAvoiddata completeness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by counting the clock signal cycles during data transmission in advance and comparing the count value with the expected value before data storage is completed. This allows the system to detect potential under-runs before they result in permanent data loss, enabling preventive measures to be taken. The counter 220 continuously monitors clock signals during the data reception process, and control logic 230 compares the accumulated count against the expected count derived from the program command, detecting discrepancies before incomplete data is committed to storage.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by continuously monitoring the clock signal count during data transmission and using this information to control the data storage process. The control logic 230 receives feedback from the counter 220 regarding the actual number of clock cycles elapsed, compares this with the expected value, and adjusts the storage operation accordingly. When an under-run is detected through this feedback mechanism, the system can issue a reset signal to clear the buffer region 240, preventing incomplete data from being stored.

Inventive Principle:
Principle #23Feedback

2Reliability

If buffer region is reset upon under-run detection to prevent incomplete data storage, then data reliability is improved, but data transmission time is increased due to retransmission

Engineering Contradiction:
Improvedata integrityVSAvoiddata retransmission time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies self-service by enabling the memory device to autonomously detect under-runs and reset its own buffer region without requiring external intervention from the controller. The control logic 230 within the memory device independently monitors the clock signal count through counter 220, compares it with the expected value, and when an under-run is detected, automatically generates and executes a reset signal to clear buffer region 240. This self-diagnosis and self-correction capability eliminates the need for the controller to detect the error and initiate retransmission, thereby reducing the time loss associated with the error handling process.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250238147A1Memory device, operating method of memory device, and storage device including memory device
Publication Date: 2025.07.24 SK HYNIX INC
  • US20250238147A1 patent drawing
  • US20250238147A1 patent drawing
  • US20250238147A1 patent drawing

AI summary

A memory device includes a cell region and a peripheral region including a buffer region. The cell region comprises a plurality of memory cells. The peripheral region receives data to be stored in the cell region and a clock signal to which the data is synchronized, and resets the buffer region in which the data is stored when it is determined that an under-run has occurred based on a count value of the clock signal.