Memory Output Buffer Calibration Using Shared ZQ Reference
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Solution Overview
Problem
Current memory systems with NAND flash memory require lengthy calibration operations for output impedance, which can be time-consuming and inefficient, especially when calibrating multiple semiconductor storage devices.
Innovation Solution
A semiconductor device architecture that includes a reference resistor and a controller to perform ZQ calibration and subsequent chip calibration operations, utilizing replica buffer circuits and output buffer controllers to calibrate output impedances efficiently, allowing for parallel calibration of multiple chips and reducing overall calibration time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional ZQ calibration operation is performed for each semiconductor storage device, then output impedance precision is maintained, but calibration time becomes excessively long
Solution Approach 1:
Multiple semiconductor storage devices are electrically connected in parallel through signal lines to a single reference resistor, allowing simultaneous calibration of multiple devices. The calibration circuit performs one calibration operation that calibrates all connected devices at once, merging what would otherwise be sequential operations into a single parallel process.
Solution Approach 2:
A single reference resistor and calibration circuit serve multiple semiconductor storage devices simultaneously, making the calibration system universal. The same calibration infrastructure (reference resistor, calibration circuit, signal lines) is shared across multiple devices, eliminating the need for separate calibration systems for each device.
2Measurement precision
If multiple chips are calibrated sequentially using traditional methods, then calibration precision is maintained, but productivity decreases
Solution Approach 1:
The patent merges multiple calibration operations into a single simultaneous operation by electrically connecting multiple semiconductor storage devices in parallel to a shared reference resistor. This allows the calibration circuit to calibrate all devices at the same time, dramatically increasing throughput while preserving precision through the shared reference standard.
3Loss of time
If parallel calibration of multiple chips is implemented, then calibration time is reduced, but device complexity increases
Solution Approach 1:
The calibration system achieves multi-functionality by enabling a single reference resistor and calibration circuit to serve multiple semiconductor storage devices simultaneously. The same hardware infrastructure performs calibration for all connected devices, reducing overall system complexity compared to having separate calibration circuits for each device while enabling parallel operation.
Data Source
AI summary
A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.