Memory Buffering with Fast Packet Information Access
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Solution Overview
Problem
Existing memory buffering systems in networking devices face inefficiencies due to the large area consumption of on-chip storage for packet length information and pointers, which complicates the retrieval of packet lengths for scheduling and transmission.
Innovation Solution
A secondary memory is used to store packet length information, mirroring the main memory, allowing efficient access and decoding of packet lengths without the need to access the main memory, using a specific encoding scheme that allocates fixed storage bits for each particle, enabling quick retrieval of packet lengths and reducing the need for multiple pointer accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If packet length information and pointers are stored on-chip with the scheduling processor chip, then packet length retrieval is fast and efficient, but the die area consumption increases significantly
Solution Approach 1:
The patent extracts packet length information from the on-chip scheduling processor chip and stores it in off-chip memory. This separation removes the memory storage burden from the chip while maintaining fast access through dedicated memory interfaces, resolving the contradiction between fast retrieval and area consumption.
Solution Approach 2:
The patent introduces an intermediary memory structure that bridges the scheduling processor and packet data storage. This intermediary layer stores packet length information and pointers, enabling fast access without requiring the information to be stored directly on the chip, thus reducing die area while maintaining performance.
2Productivity
If pointers are stored on-chip to access packet data in off-chip memory, then packet data access is efficient, but the die area consumption increases
Solution Approach 1:
The patent extracts pointer storage from the on-chip scheduling processor and places it in off-chip memory. This allows the chip to maintain its scheduling functions while off-chip memory handles the pointer storage, enabling efficient packet data access without consuming chip area.
Solution Approach 2:
The off-chip memory structure serves multiple functions: storing packet data, storing packet length information, and storing pointers. This multi-functional approach eliminates the need for separate on-chip storage structures, maintaining access efficiency while reducing die area.
3Area of stationary object
If packet length information is stored in off-chip memory with pointers, then die area is reduced, but multiple pointer accesses are required to retrieve packet lengths
Solution Approach 1:
The patent merges packet length information and pointers into a unified memory structure with direct addressing capabilities. This combination allows the scheduling processor to access packet length information through a single memory operation rather than following multiple pointers, reducing retrieval time while maintaining compact storage.
Solution Approach 2:
The patent implements preliminary action by pre-organizing packet length information and pointers in a structured off-chip memory layout that enables direct access. This pre-arranged structure eliminates the need for sequential pointer chasing during packet processing, significantly reducing retrieval time.
Data Source
AI summary
A networking device employing memory buffering in which a first memory is logically configured into blocks, and the blocks are logically configured into particles, where a second memory is configured to mirror the first memory in which a fixed number of bits in the second memory are allocated for each particle in the first memory so that scheduling and datagram lengths of packets stored in the first memory may be stored in the second memory. Other embodiments are described and claimed.