Memory Building Blocks for Automatic ASIC Design
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Solution Overview
Problem
Traditional memory design is time-consuming and inflexible, relying on manual schematic and layout, with limited flexibility in memory interface and specific applications, and current ASIC design tools are not suited for memory design due to their focus on digital circuits.
Innovation Solution
The development of memory building blocks that can be used with conventional ASIC design tools to automatically generate memory arrays, converting analog memory cells to digital standard cells with programmable control circuits and flexible interfaces, allowing for user-specified timing specifications and reduced design turn-around time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual schematic and layout methods are used for memory design, then design flexibility and customization are improved, but design time and labor effort increase significantly
Solution Approach 1:
The memory design is segmented into standardized building blocks (memory cells, bit lines, word lines, sense amplifiers) that can be independently designed and then automatically assembled by EDA tools, resolving the contradiction between manual customization flexibility and automated design time reduction
Solution Approach 2:
The invention changes the parameter representation from manual schematic diagrams to structured data formats with defined parameters (dimensions, electrical characteristics, connectivity), enabling automated processing while maintaining design flexibility through parameter customization
2Loss of time
If pre-defined control circuits are used in compiler-based memory design, then design time is reduced, but flexibility and adaptability to different applications are lost
Solution Approach 1:
The control circuit parameters are made dynamic and configurable rather than fixed, allowing the same automated design flow to adapt to different memory interfaces and applications by modifying parameters without requiring pre-defined fixed designs
Solution Approach 2:
The building block library is designed to be universal and application-agnostic, enabling the same standardized blocks to serve multiple different memory interface requirements through parameter configuration rather than requiring application-specific custom designs
3Ease of manufacture
If ASIC design tools focused on digital circuits are used for memory design, then tool availability is improved, but design precision and suitability for memory-specific requirements deteriorate
Solution Approach 1:
The invention introduces an intermediary layer of memory-specific building blocks and design rules that bridge between general-purpose ASIC EDA tools and memory-specific design requirements, enabling existing tools to achieve memory design precision through standardized interfaces and parameters
Data Source
AI summary
The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.