Semiconductor Memory Internal Signal Generation for Burn-in Test
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Solution Overview
Problem
Conventional burn-in tests for semiconductor memory devices are time-consuming due to the slow operation speed of external test equipment, which prolongs the frequency of the external clock and thus extends the test duration.
Innovation Solution
A semiconductor memory device that internally generates command signals in synchronization with the rising edge of the external clock, enabling it to perform a burn-in test more efficiently by generating internal active, write, and precharge signals in response to preset combinations of external commands, thereby reducing the test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the external test equipment operates at a slow speed with a low external clock frequency to ensure reliable signal transmission, then the burn-in test can be performed with stable external command signals, but the burn-in test time is significantly lengthened
Solution Approach 1:
The patent introduces an internal clock signal as an intermediary between the external clock and the internal command signal generation. The internal clock operates at a higher frequency than the external clock, allowing internal commands to be generated faster while the external clock maintains its stable, low-frequency operation for reliable signal transmission. This mediator enables the system to decouple the timing requirements of external communication from internal processing.
Solution Approach 2:
The patent segments the command signal generation into two distinct stages: external clock-driven stages for reliable communication and internal clock-driven stages for fast internal processing. By dividing the timing control into external and internal domains with different clock frequencies, the system achieves both reliable external signal transmission and fast internal operation, resolving the contradiction between reliability and test time.
2Productivity
If the external clock frequency is increased to speed up the burn-in test, then the burn-in test time is reduced, but the external test equipment operation speed becomes a limiting factor
Solution Approach 1:
The patent adds a new dimension to the timing system by introducing an internal clock frequency domain that is independent of the external clock frequency. Instead of simply increasing the external clock frequency to improve test speed, the invention creates a multi-frequency domain system where internal operations can proceed at a higher frequency than external operations, thereby bypassing the external equipment speed limitation.
Solution Approach 2:
The system dynamically switches between external clock synchronization for command reception and internal clock synchronization for command execution. This dynamic timing adjustment allows the memory device to adapt its internal operation speed independently of the external test equipment speed, enabling faster burn-in testing without being constrained by external equipment limitations.
3Measurement precision
If internal command signals are generated in synchronization with the rising edge of the external clock, then the burn-in test can be performed with precise timing control, but the test time remains dependent on the external clock frequency
Solution Approach 1:
The internal clock signal serves as a mediator that decouples the timing precision requirement from the external clock frequency constraint. By using the internal clock to generate internal command signals, the system maintains precise timing control (inherited from the external clock's rising edge synchronization) while operating at a higher frequency, thus reducing test time without sacrificing timing precision.
Data Source
AI summary
A semiconductor memory device includes an internal signal generation block configured to generate a control signal which is enabled from a generation time of an internal active signal enabled if it is determined that a combination of external commands in synchronization with a rising edge of an external clock inputted from an outside is a preset combination, to a disable time an internal idle signal; and an internal command signal generation block configured to generate an internal write signal if it is determined that a combination of counting signals counted during an enable period of the control signal is a first combination and generate an internal precharge signal if it is determined that the combination of the counting signals is a second combination.