Memory Burst Read Termination via Dual Command Signals
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Solution Overview
Problem
In semiconductor systems, the existing burst read operation termination mechanism can lead to violations of defined time intervals, causing invalid data output due to premature termination of burst read operations by the memory controller, which may result in malfunction between the memory controller and the memory apparatus.
Innovation Solution
The memory controller provides multiple third command address signals to the memory apparatus to ensure proper termination of the burst read operation, enabling and disabling a reset signal to initialize internal circuits, thereby maintaining data integrity and preventing invalid data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller terminates the burst read operation by providing a third command address signal, then the burst read operation can be stopped, but the internal circuit may not be fully initialized causing invalid data output
Solution Approach 1:
The patent applies preliminary action by continuously enabling the reset signal from the moment the third command address signal is first received until it is secondly received. This ensures the internal circuit is fully initialized before the burst read operation terminates, preventing invalid data output while maintaining reliable operation
Solution Approach 2:
The reset signal acts as an intermediary mechanism that bridges the termination of the burst read operation and the initialization of the internal circuit. By continuously maintaining the reset signal enabled during the critical transition period, the patent ensures proper initialization without compromising data integrity
2Reliability
If the reset signal is continuously enabled during burst read operation termination, then complete initialization is ensured, but the operation time is extended
Solution Approach 1:
The patent employs periodic action through the use of the third command address signal being provided at specific intervals - first received to start continuous reset, and secondly received to end continuous reset. This periodic signaling mechanism ensures complete initialization while controlling the duration of the extended operation
Data Source
AI summary
A semiconductor system includes a memory controller and a memory apparatus. The memory controller provides at least first to third command address signals. The memory apparatus performs a burst read operation based on the first and second command address signals, and terminates the burst read operation by receiving the third command address signal twice. The memory apparatus continuously initializes an internal circuit that is performing the burst read operation in a section the third command address signal is received twice.