Main Memory Bus Bridging for Co-Processor I/O Bottlenecks

The memory bus is designed to serve multiple functions: it continues to connect the CPU to system memory while also enabling co-processors and I/O devices to interface directly with the memory system. This multi-functionality allows the same high-bandwidth bus to serve both traditional memory access and accelerated I/O operations, resolving the contradiction between improved speed and increased complexity.

The patent introduces a memory interface controller or bridge that mediates between the memory bus and co-processors/I/O devices. This intermediary component manages the interface complexity, allowing devices to access the high-bandwidth memory bus without requiring the entire system architecture to become more complex. The mediator handles protocol conversion and access arbitration.

The system architecture segments the communication paths by providing dedicated memory bus access to co-processors for data-intensive operations while maintaining separate I/O bus connections for control and configuration. This segmentation allows fast processing on the memory bus without being bottlenecked by the slower I/O bus, resolving the contradiction between processing capability and communication delay.

The patent adds a new dimension to the communication architecture by introducing a second communication path (memory bus) that operates in parallel with the traditional I/O bus. Co-processors can utilize the high-bandwidth memory bus dimension for data transfer while the I/O bus handles control functions, eliminating the bottleneck and allowing processing capability to scale without proportional increases in communication delay.

The memory interface controller implements feedback mechanisms that monitor bus utilization and dynamically adjust access priorities and timing for different devices. When the memory bus becomes congested, the controller receives feedback about queue depths and transfer completion status, then adjusts arbitration decisions to prevent overload and maintain reliable operation, resolving the contradiction between enhanced speed and maintained reliability.

The system employs periodic bus arbitration schemes where access rights to the memory bus are granted in regular time slots or cycles to different devices. This periodic action prevents any single device from monopolizing the bus, ensures fair resource distribution, and maintains predictable performance characteristics even under heavy load, thereby preserving reliability while enabling high-speed transfers.