Memory Bus Broadcast Architecture for Chip Area Reduction
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Solution Overview
Problem
Parallel processing in data processors is hindered by long routing times and inefficient use of memory space due to the need for dedicated broadcast buses, which increases complexity and reduces marginal increases in operating speeds.
Innovation Solution
Eliminating the need for a dedicated broadcast bus by transmitting data from a controller to a memory and then to processor units using existing data buses, thereby reusing memory buses and reducing chip real estate and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a dedicated broadcast bus is used to transmit data to multiple processor units, then data transmission to all processor units can be achieved, but routing time increases and device complexity increases
Solution Approach 1:
The memory data bus is designed to serve multiple functions: it transmits both normal data between memory and processor units, and also functions as a broadcast bus for transmitting identical data to multiple processor units simultaneously. This eliminates the need for a separate dedicated broadcast bus, reducing routing complexity while maintaining fast data transmission capability.
Solution Approach 2:
The patent combines the broadcast data transmission function with the existing memory data bus infrastructure. By merging these functions into a single bus system, the patent reduces the total number of routing lines required, simplifies the overall device architecture, and decreases routing time while achieving fast data distribution to multiple processor units.
2Reliability
If constants are stored in each computational unit's memory space, then broadcast data can be accessed locally, but memory space is wasted
Solution Approach 1:
The memory data bus serves dual purposes: it acts as both a normal data transmission bus and a broadcast bus. By making the bus multi-functional, the patent eliminates the need for duplicate constant storage in each computational unit's memory, thereby saving memory space while maintaining reliable data access through the shared bus infrastructure.
Solution Approach 2:
Instead of storing constant data in each computational unit's local memory (creating multiple copies), the patent uses the memory data bus to broadcast the same data to multiple processor units simultaneously. This approach creates functional copies through the transmission medium rather than through duplicate storage, preserving memory space while ensuring data availability.
3Productivity
If more routing lines are added to broadcast data to computational units, then data transmission capability improves, but chip area increases
Solution Approach 1:
The memory data bus is designed to perform multiple functions including normal data transmission and broadcast data distribution. By making the existing bus multi-functional, the patent achieves enhanced data transmission capability to multiple processor units without adding more physical routing lines, thereby maintaining productivity while reducing chip area requirements.
Solution Approach 2:
The patent changes the operational parameters of the existing memory data bus to enable broadcast functionality. By modifying how the bus operates (transmitting identical data to multiple destinations simultaneously), the patent achieves improved data transmission capability without increasing the physical number of routing lines, thus avoiding additional chip area consumption.
Data Source
AI summary
A data processor apparatus and memory interface comprises a memory, a plurality of memories, an interface for controlling access to the memories by a device, and an identifier identifying at least a memory location in one memory and a memory location in another memory. The interface is responsive to the identifier to condition the memory locations for receiving data and/or for transferring data therefrom. This arrangement eliminates the need for a dedicated broadcast bus from the array controller to each processor unit (PU), which thereby enables the area/space required to accommodate the data processor to be significantly reduced.