Memory Device Communications Bus for Controller Initiation
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Solution Overview
Problem
Current memory systems are limited in their ability for memory devices to initiate communications with the memory controller, leading to inefficiencies in bandwidth usage and restricted capabilities for bulk information transfer, particularly in controller-centric architectures.
Innovation Solution
The introduction of a separate communications bus that allows memory devices to initiate communications with the memory controller and other devices, using a token-based protocol and potentially different clock signals, enabling bulk data transfer without tying up command/address and data buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a controller-centric architecture is used for memory systems, then the memory controller can manage communications, but the memory devices cannot initiate communications leading to restricted capabilities for bulk information transfer
Solution Approach 1:
The patent segments the communication functionality by introducing a separate communications bus distinct from the command/address bus and data bus. This allows memory devices to initiate communications independently without interfering with the existing controller-centric command structure, thereby enhancing adaptability while maintaining architectural clarity.
Solution Approach 2:
The patent introduces an intermediary token-based protocol on the communications bus that mediates between memory devices and the memory controller. This intermediary mechanism enables memory devices to initiate bulk information transfer requests without directly disrupting the command/address bus operations, resolving the contradiction between enhanced communication capability and architectural complexity.
2Productivity
If the command/address bus and data bus are used for all communications, then existing buses are utilized, but bandwidth is inefficiently used and bulk information transfer is restricted
Solution Approach 1:
The patent segments the communication infrastructure into three distinct buses: command/address bus for control signals, data bus for data transfer, and a new communications bus for bulk information transfer and device-initiated communications. This segmentation allows each bus to be optimized for its specific function, improving overall bandwidth utilization without requiring a complete restructuring of the existing bus system.
Solution Approach 2:
The communications bus is designed with multi-functionality to handle various types of bulk information transfer including reliability information, refresh information, and device-initiated communications. This universal bus can operate independently alongside the command/address and data buses, enhancing productivity without adding significant complexity to the overall bus structure.
3Quantity of substance
If memory devices initiate bulk communications, then bulk information transfer capability improves, but additional communication infrastructure is required
Solution Approach 1:
The patent segments communication protocols into two categories: traditional command/address protocols for controller-initiated operations, and a new token-based protocol on the communications bus for device-initiated bulk transfers. This segmentation allows bulk information transfer to occur without interfering with existing communication infrastructure, achieving increased information transfer volume with minimal additional complexity.
Solution Approach 2:
The token-based protocol on the communications bus enables memory devices to self-service by initiating bulk information transfer requests autonomously without requiring continuous controller intervention. Devices can independently manage reliability information reporting, refresh operations, and other bulk communications, thereby improving information transfer capability while keeping the additional infrastructure requirements manageable.
Data Source
AI summary
Memory systems with a communications bus (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a memory device includes an input/output terminal separate from data terminals of the memory device. The input/output terminal can be operably connected to a memory controller via a communications bus. The memory device can be configured to initiate a communication with the memory controller by outputting a signal via the input/output terminal and/or over the communications bus. The memory device can be configured to output the signal in accordance with a clock signal that is different from a second clock signal used to output or receive data signals via the data terminals. In some embodiments, the memory device is configured to initiate communications over the communication bus only when it possesses a communication token. The communication token can be transferred between memory devices operably connected to the communications bus.