Memory-Bus Converged Storage for Low-Latency Non-Volatile Access
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Solution Overview
Problem
Current storage systems face inefficiencies due to higher latency associated with serial bus protocols for accessing non-volatile memory, which limits the optimization of storage operations and decreases system efficiency.
Innovation Solution
A high-density converged storage system is implemented where volatile and non-volatile memory are co-located on the same storage device, with a simplified controller managing data paths directly between them, eliminating the need for serial bus protocols and reducing latency by using a memory bus for data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial bus protocols (PCIe, NVMe, SAS/SATA) are used to access non-volatile memory, then storage devices can be connected to server CPU, but the latency increases to 4-25 μs compared to 1 μs for memory bus access
Solution Approach 1:
The patent combines volatile memory and non-volatile memory into a single storage device that interfaces with the server CPU through a single memory bus connection. This merging eliminates the need for separate serial bus connections for each memory type, allowing data to be transferred directly between volatile and non-volatile memory through the memory bus without the latency overhead of serial bus protocols.
Solution Approach 2:
The volatile memory within the storage device acts as an intermediary between the memory bus and non-volatile memory. Data received from the memory bus is first stored in volatile memory, then transferred to non-volatile memory through the controller. This intermediary approach allows the system to leverage the high-speed memory bus while still providing persistent storage, achieving low-latency access without sacrificing data durability.
2Reliability
If non-volatile memory is accessed via serial bus protocols, then data can be stored persistently, but the higher latency caps optimization of storage operations
Solution Approach 1:
The patent merges volatile and non-volatile memory capabilities into a unified storage device that presents a single interface to the system. This combination allows storage operations to be optimized using memory bus speeds while maintaining data persistence through non-volatile memory, removing the latency cap that previously limited storage operation optimization.
Solution Approach 2:
The patent changes the fundamental parameter of data transfer speed by routing data through the memory bus instead of serial bus protocols. This parameter change from serial communication to parallel memory bus communication dramatically increases transfer speeds and enables storage operations to be optimized without being capped by protocol limitations.
3Adaptability or versatility
If volatile memory and non-volatile memory are separated into different storage devices, then each device can be optimized independently, but data transfer between them requires additional interfaces and increases latency
Solution Approach 1:
The patent combines volatile and non-volatile memory into a single integrated storage device, eliminating the need for data transfer between separate devices. Both memory types coexist within the same device boundary, allowing data to be transferred internally through the controller without requiring external interface connections, thus eliminating the latency associated with inter-device communication.
Data Source
AI summary
One embodiment facilitates a high-density converged storage system. During operation, the system receives, by a volatile memory of a storage device via a memory bus, data to be stored in a non-volatile memory of the same storage device. The system writes, by a controller of the storage device, the data directly to the non-volatile memory via the volatile memory, e.g., without using a serial bus protocol.