Semiconductor Memory Bus Current Reduction via Bit Inversion
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing Read/Write Bus (RWBS) charging/discharging current without increasing operating current, circuit size, or reducing operating speed, particularly when transitioning from four-bit parallel to time division transfer methods.
Innovation Solution
A data transfer device that includes a flag generation circuit to indicate bit inversion, an encoding circuit to encode bit sequences based on the flag, and a decoding circuit to decode the sequences, allowing for sequential parallel transfer through a reduced number of buses using 4:2 parallel-to-serial conversion, thereby minimizing RWBS transients and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If time division transfer method using 4:2 P/S conversion is used, then the number of buses is reduced, but the RWBS charging/discharging current is not necessarily reduced
Solution Approach 1:
The flag generation circuit performs preliminary analysis of data patterns before data transfer to determine whether bit inversion is needed. By predicting data transitions in advance and setting inversion flags accordingly, the system prepares the optimal transfer mode before actual data transmission, thereby reducing unnecessary bus transients and charging/discharging current.
Solution Approach 2:
The invention introduces bit inversion as a complementary transfer method. Instead of always using non-inverted data transfer, the system inverts bits based on predicted data patterns and uses inversion flags to indicate when inversion should occur at the receiver. This alternative approach reduces the number of bus transients by exploiting data pattern characteristics.
2Loss of energy
If majority decision circuit is added to reduce RWBS charging/discharging current, then the current is reduced, but the operating current increases
Solution Approach 1:
The invention extracts only the essential function of the majority decision circuit (determining data pattern characteristics) and implements it through a simplified flag generation circuit that analyzes data patterns and sets inversion flags. This extracted approach achieves the current reduction benefit without incorporating the full complexity and power consumption of a complete majority decision circuit.
Solution Approach 2:
Instead of using a complex, power-consuming majority decision circuit, the invention employs a simpler, lower-power flag generation circuit that performs the necessary data pattern analysis. The simplified circuit consumes less operating current while achieving the same goal of reducing RWBS charging/discharging current through intelligent data transfer mode selection.
3Loss of energy
If majority decision circuit is added to reduce RWBS charging/discharging current, then the current is reduced, but the circuit size increases
Solution Approach 1:
The invention extracts only the essential function of the majority decision circuit (determining data pattern characteristics) and implements it through a simplified flag generation circuit that analyzes data patterns and sets inversion flags. This extracted approach achieves the current reduction benefit without incorporating the full complexity and area of a complete majority decision circuit.
4Loss of energy
If majority decision circuit is added to reduce RWBS charging/discharging current, then the current is reduced, but the operating speed is reduced
Solution Approach 1:
The flag generation circuit performs preliminary data pattern analysis in parallel with data transfer operations, setting inversion flags before the actual data transfer begins. This preliminary action ensures that the data transfer path is optimized in advance, avoiding any speed penalty during the actual data transmission phase.
Solution Approach 2:
The invention dynamically selects the data transfer mode (inverted or non-inverted) based on real-time data pattern analysis. The flag generation circuit continuously monitors data patterns and adjusts the inversion flag settings accordingly, allowing the system to adapt to varying data characteristics without reducing operating speed.
Data Source
AI summary
Data transfer bus charging/discharging current is reduced in a semiconductor memory device. In a data transfer device that sequentially transfers bit sequences in parallel through a plurality of buses from a transmit unit 10 to a receive unit 20, the transmit circuit 10 includes a flag generation circuit 11 and an encoding circuit 12. The flag generation circuit 11 generates a flag indicating whether bit inversion has occurred in consecutive bits in each of the bit sequences to be transferred through the buses and transmits the generated flag to the receive unit 20. The encoding circuit 12 encodes the bit sequences based on the flag, for transmission to the receive unit 20. The receive unit includes a decoding circuit 21 that decodes the bit sequences based on the bit sequences and the flag.