Memory Bus Drive Defect Detection via Pull-Up Resistor

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Solution Overview

Problem

In memory bus drive systems, defects such as bond wire breaks or shorts can cause the bus to be terminated to ground, making it difficult for host devices to distinguish between data communication and defects, leading to increased failure-in-time (FIT) rates beyond industry standards.

Innovation Solution

Incorporating a resistive component between the memory device's DQ pins and the power supply, which operates the bus in a high resistance state when no data is being communicated, allowing the host device to differentiate between data communication and defects by detecting the bus state.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the bus is terminated to ground due to defects (bond wire breaks or shorts), then the system can detect the defect condition, but the host device cannot distinguish between defect-induced grounding and legitimate data communication, leading to increased FIT rates

Engineering Contradiction:
ImproveFIT rateVSAvoiddefect detection accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

A pull-up resistor is introduced as an intermediary component between the DQ pin and the power supply. This resistor creates a predictable high-impedance state when no data is being communicated, allowing the host device to distinguish between defect-induced grounding and legitimate data communication by monitoring bus state transitions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The pull-up resistor is configured to establish a known initial state (high-impedance/floating state) on the bus before data communication begins. This preliminary state setup enables the host device to detect defects by observing unexpected transitions from this known state, improving defect detection accuracy while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If the bus operates in a high resistance state when no data is communicated, then the host device can differentiate between data communication and defects, but this requires additional resistive components and circuitry

Engineering Contradiction:
Improvebus state detection accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

A pull-up resistor is introduced as an intermediary component between the DQ pin and the power supply. This resistor creates a predictable high-impedance state when no data is being communicated, allowing the host device to distinguish between defect-induced grounding and legitimate data communication by monitoring bus state transitions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The pull-up resistor automatically establishes the high-impedance state without requiring additional control circuitry or active components. The resistor passively pulls the bus to a known state based on the absence of data communication, simplifying the overall circuit design while enabling accurate bus state detection.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables the host device to accurately determine whether the memory device is communicating data or experiencing a defect, thereby reducing the FIT rate and ensuring compliance with industry standards.

Implementation Method 1

a resistive component... coupled with a power supply of the memory device and configured to cause a bus to operate in a first state based on an absence of data communicated over the bus

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS11714576B2Memory bus drive defect detection
Publication Date: 2023.08.01 MICRON TECHNOLOGY INC
  • US11714576B2 patent drawing
  • US11714576B2 patent drawing
  • US11714576B2 patent drawing

AI summary

Methods, systems, and devices for memory bus drive defect detection and related operations are described. A controller coupled with a memory array may receive a command for data. The memory array may include one or more pins for communicating data to and from the memory array, in response to the command. The controller may transmit to the memory array, over a bus that is coupled with the controller and the pins, the command. The controller may detect, based at least in part on a resistor coupled with the bus and a power supply of the memory array, that the bus is operating in a first state after transmitting the command. The first state may comprise a voltage that is relatively higher than a voltage of the second state. The controller may determine a defect associated with the bus or the pin based on detecting the bus in the first state.