Memory Bus State Detection for Floating-Bus Data Integrity
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Solution Overview
Problem
Memory systems experience increased failure rates due to packaging errors that cause buses to enter or remain in a floating state, leading to indeterminate signals and improper data handling by the host device, which can result in invalid data usage and system failures.
Innovation Solution
Configuring a control signal, such as a syndrome check signal, to indicate errors in data signals when the bus is idle by inverting its voltage state to match the floating bus voltage, allowing the host device to discard invalid data and reduce failure rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the bus is left in a floating state during idle periods, then power consumption is reduced and signal lines remain undriven, but indeterminate signals are generated and data integrity is compromised
Solution Approach 1:
The memory device proactively drives the bus with an idle state indicator signal before the host device attempts to read data, preventing the bus from entering a floating state. This preliminary action ensures the bus maintains a defined voltage level, eliminating indeterminate signals while keeping power consumption low through controlled driving rather than continuous active state maintenance
Solution Approach 2:
An idle state indicator signal is introduced as an intermediary between the memory device and host device to communicate bus status. This intermediary signal allows the host device to recognize when the bus is idle and discard potential invalid data, resolving the data integrity issue without requiring the bus to remain actively driven
2Reliability
If the bus is continuously driven to maintain defined voltage levels, then signal stability is improved and indeterminate states are prevented, but power consumption increases
Solution Approach 1:
Instead of continuous driving, the memory device periodically drives the bus with idle state indicator signals during idle periods. This periodic action maintains signal stability only when necessary (during idle states), allowing the bus to float during active data transmission when power consumption is already elevated, thus optimizing the balance between reliability and energy loss
Solution Approach 2:
The memory device preemptively drives the bus with an idle state indicator before the host device samples the data lines, ensuring the bus is in a defined state only when needed. This preliminary driving action prevents indeterminate signals without maintaining continuous driving, reducing power consumption compared to persistent bus activation
3Productivity
If the host device reads data from the bus without verification, then data access speed is maximized, but invalid data may be used causing system failures
Solution Approach 1:
The idle state indicator signal provides feedback to the host device about the bus state. The host device monitors this indicator and uses it to determine whether data on the bus is valid or should be discarded. This feedback mechanism enables the host to maintain high data access speed by quickly identifying valid data while preventing system failures through automatic discarding of invalid data from floating bus states
Solution Approach 2:
The memory device preemptively places an idle state indicator on the bus before the host device attempts to read data. This preliminary indication allows the host device to quickly verify data validity without lengthy verification procedures, maintaining high access speed while preventing invalid data usage through advance warning of bus idle states
Data Source
AI summary
Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.